Configures the megachips-stdpxxxx-ge-b850v3-fw bridges on the GE
B850v3 dts file.
Cc: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
Cc: Martyn Welch <martyn.we...@collabora.co.uk>
Cc: Martin Donnelly <martin.donne...@ge.com>
Cc: Javier Martinez Canillas <jav...@dowhile0.org>
Cc: Enric Balletbo i Serra <enric.balle...@collabora.com>
Cc: Philipp Zabel <p.za...@pengutronix.de>
Cc: Rob Herring <r...@kernel.org>
Cc: Fabio Estevam <fabio.este...@nxp.com>
Signed-off-by: Peter Senna Tschudin <peter.se...@collabora.com>
---
arch/arm/boot/dts/imx6q-b850v3.dts | 68 ++++++++++++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts
b/arch/arm/boot/dts/imx6q-b850v3.dts
index b237429..3ec54da 100644
--- a/arch/arm/boot/dts/imx6q-b850v3.dts
+++ b/arch/arm/boot/dts/imx6q-b850v3.dts
@@ -72,6 +72,13 @@
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
status = "okay";
+
+ port@4 {
+ reg = <4>;
+ lvds0_out: endpoint {
+ remote-endpoint = <&stdp4028_in>;
+ };
+ };
};
};
@@ -146,3 +153,64 @@
&usdhc2 {
status = "disabled";
};
+
+&mux2_i2c2 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ stdp4028@73 {
+ compatible = "megachips,stdp4028-ge-b850v3-fw";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0x73>;
+
+ interrupt-parent = <&gpio2>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ stdp4028_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ stdp4028_out: endpoint {
+ remote-endpoint = <&stdp2690_in>;
+ };
+ };
+ };
+ };
+
+ stdp2690@72 {
+ compatible = "megachips,stdp2690-ge-b850v3-fw";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0x72>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ stdp2690_in: endpoint {
+ remote-endpoint = <&stdp4028_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ stdp2690_out: endpoint {
+ /* Connector for external display */
+ };
+ };
+ };
+ };
+};
--
2.5.5
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