This reverts commit 01338bb82fed40a6a234c2b36a92367c8671adf0. With clock improvements in place, this seems to be no longer necessary. Set the CLRSIPO to default setting recommended by manufacturer.
Signed-off-by: Marek Vasut <ma...@denx.de> --- Cc: Andrzej Hajda <andrzej.ha...@intel.com> Cc: Daniel Vetter <dan...@ffwll.ch> Cc: David Airlie <airl...@gmail.com> Cc: Jernej Skrabec <jernej.skra...@gmail.com> Cc: Jonas Karlman <jo...@kwiboo.se> Cc: Laurent Pinchart <laurent.pinch...@ideasonboard.com> Cc: Lucas Stach <l.st...@pengutronix.de> Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com> Cc: Maxime Ripard <mrip...@kernel.org> Cc: Neil Armstrong <neil.armstr...@linaro.org> Cc: Robert Foss <rf...@kernel.org> Cc: Thomas Zimmermann <tzimmerm...@suse.de> Cc: dri-devel@lists.freedesktop.org Cc: ker...@dh-electronics.com --- V2: No change V3: No change --- drivers/gpu/drm/bridge/tc358767.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 743bf1334923d..2b035a136a6e5 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -1356,10 +1356,10 @@ static int tc_dsi_rx_enable(struct tc_data *tc) u32 value; int ret; - regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 25); - regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 25); - regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 25); - regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 25); + regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5); + regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5); + regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5); + regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5); regmap_write(tc->regmap, PPI_D0S_ATMR, 0); regmap_write(tc->regmap, PPI_D1S_ATMR, 0); regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE); -- 2.43.0