[PATCH v3 2/6] drm/bridge: tc358767: Use tc_pxl_pll_calc() to correct adjusted_mode clock

[Marek Vasut]

Use tc_pxl_pll_calc() to find out the exact clock frequency generated by the
Pixel PLL. Use the Pixel PLL frequency as adjusted_mode clock frequency and
pass it down the display pipeline to obtain exactly this frequency on input
into this bridge.

The precise input frequency that matches the Pixel PLL frequency is
important for this bridge, as if the frequencies do not match, the
bridge does suffer VFIFO overruns or underruns.

Signed-off-by: Marek Vasut <ma...@denx.de>
---
Cc: Andrzej Hajda <andrzej.ha...@intel.com>
Cc: Daniel Vetter <dan...@ffwll.ch>
Cc: David Airlie <airl...@gmail.com>
Cc: Jernej Skrabec <jernej.skra...@gmail.com>
Cc: Jonas Karlman <jo...@kwiboo.se>
Cc: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
Cc: Lucas Stach <l.st...@pengutronix.de>
Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
Cc: Maxime Ripard <mrip...@kernel.org>
Cc: Neil Armstrong <neil.armstr...@linaro.org>
Cc: Robert Foss <rf...@kernel.org>
Cc: Thomas Zimmermann <tzimmerm...@suse.de>
Cc: dri-devel@lists.freedesktop.org
Cc: ker...@dh-electronics.com
---
V2: - Use mode clock as input into tc_pxl_pll_calc() to avoid
      accumulating rounding error
V3: No change
---
 drivers/gpu/drm/bridge/tc358767.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/bridge/tc358767.c 
b/drivers/gpu/drm/bridge/tc358767.c
index cbb342d811ac3..20be21660ba76 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -1619,6 +1619,18 @@ static int tc_dpi_atomic_check(struct drm_bridge *bridge,
                               struct drm_crtc_state *crtc_state,
                               struct drm_connector_state *conn_state)
 {
+       struct tc_data *tc = bridge_to_tc(bridge);
+       int adjusted_clock = 0;
+       int ret;
+
+       ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk),
+                             crtc_state->mode.clock * 1000,
+                             &adjusted_clock, NULL);
+       if (ret)
+               return ret;
+
+       crtc_state->adjusted_mode.clock = adjusted_clock / 1000;
+
        /* DSI->DPI interface clock limitation: upto 100 MHz */
        if (crtc_state->adjusted_mode.clock > 100000)
                return -EINVAL;
@@ -1631,6 +1643,18 @@ static int tc_edp_atomic_check(struct drm_bridge *bridge,
                               struct drm_crtc_state *crtc_state,
                               struct drm_connector_state *conn_state)
 {
+       struct tc_data *tc = bridge_to_tc(bridge);
+       int adjusted_clock = 0;
+       int ret;
+
+       ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk),
+                             crtc_state->mode.clock * 1000,
+                             &adjusted_clock, NULL);
+       if (ret)
+               return ret;
+
+       crtc_state->adjusted_mode.clock = adjusted_clock / 1000;
+
        /* DPI->(e)DP interface clock limitation: upto 154 MHz */
        if (crtc_state->adjusted_mode.clock > 154000)
                return -EINVAL;
-- 
2.43.0