Exynos7870's DSIM has separate registers for LINK and DPHY status. This is in contrast to other devices in the driver which use a single register for both.
Add their respective entries in the register list. Devices having a single status register have been assigned the same offset for both entries. Signed-off-by: Kaustabh Chakraborty <[email protected]> --- drivers/gpu/drm/bridge/samsung-dsim.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 0014c497e3fe7d8349a119dbdda30d65d816cccf..c418d9e30222ec47eec05bbdefef3df8b7fec3c4 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -29,7 +29,7 @@ /* returns true iff both arguments logically differs */ #define NEQV(a, b) (!(a) ^ !(b)) -/* DSIM_STATUS */ +/* DSIM_DPHY_STATUS */ #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) #define DSIM_STOP_STATE_CLK BIT(8) #define DSIM_TX_READY_HS_CLK BIT(10) @@ -238,7 +238,8 @@ enum samsung_dsim_transfer_type { }; enum reg_idx { - DSIM_STATUS_REG, /* Status register */ + DSIM_LINK_STATUS_REG, /* Link status register */ + DSIM_DPHY_STATUS_REG, /* D-PHY status register */ DSIM_SWRST_REG, /* Software reset register */ DSIM_CLKCTRL_REG, /* Clock control register */ DSIM_TIMEOUT_REG, /* Time out register */ @@ -263,7 +264,8 @@ enum reg_idx { }; static const unsigned int exynos_reg_ofs[] = { - [DSIM_STATUS_REG] = 0x00, + [DSIM_LINK_STATUS_REG] = 0x00, + [DSIM_DPHY_STATUS_REG] = 0x00, [DSIM_SWRST_REG] = 0x04, [DSIM_CLKCTRL_REG] = 0x08, [DSIM_TIMEOUT_REG] = 0x0c, @@ -287,7 +289,8 @@ static const unsigned int exynos_reg_ofs[] = { }; static const unsigned int exynos5433_reg_ofs[] = { - [DSIM_STATUS_REG] = 0x04, + [DSIM_LINK_STATUS_REG] = 0x04, + [DSIM_DPHY_STATUS_REG] = 0x04, [DSIM_SWRST_REG] = 0x0C, [DSIM_CLKCTRL_REG] = 0x10, [DSIM_TIMEOUT_REG] = 0x14, @@ -689,7 +692,7 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, dev_err(dsi->dev, "PLL failed to stabilize\n"); return 0; } - reg = samsung_dsim_read(dsi, DSIM_STATUS_REG); + reg = samsung_dsim_read(dsi, DSIM_LINK_STATUS_REG); } while ((reg & DSIM_PLL_STABLE) == 0); dsi->hs_clock = fout; @@ -965,7 +968,7 @@ static int samsung_dsim_init_link(struct samsung_dsim *dsi) return -EFAULT; } - reg = samsung_dsim_read(dsi, DSIM_STATUS_REG); + reg = samsung_dsim_read(dsi, DSIM_DPHY_STATUS_REG); if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) != DSIM_STOP_STATE_DAT(lanes_mask)) continue; -- 2.49.0
