On Sun, Jul 20, 2025 at 05:46:12PM +0530, Akhil P Oommen wrote:
> Add a new quirk to denote IFPC (Inter-Frame Power Collapse) support
> for a gpu. Based on this flag send the feature ctrl hfi message to
> GMU to enable IFPC support.
> 
> Signed-off-by: Akhil P Oommen <akhi...@oss.qualcomm.com>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gmu.c   |  5 +++--
>  drivers/gpu/drm/msm/adreno/a6xx_hfi.c   | 33 
> +++++++++++++++++++++++++++------
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h |  1 +
>  3 files changed, 31 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c 
> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 
> 4d6c70735e0892ed87d6a68d64f24bda844e5e16..3bbcc78179c1cf1bfa21ff097e9350eb2f554011
>  100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -1961,8 +1961,9 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct 
> device_node *node)
>       if (ret)
>               return ret;
>  
> -     /* Fow now, don't do anything fancy until we get our feet under us */
> -     gmu->idle_level = GMU_IDLE_STATE_ACTIVE;
> +     /* Set GMU idle level */
> +     gmu->idle_level = (adreno_gpu->info->quirks & ADRENO_QUIRK_IFPC) ?
> +             GMU_IDLE_STATE_IFPC : GMU_IDLE_STATE_ACTIVE;
>  
>       pm_runtime_enable(gmu->dev);
>  
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c 
> b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> index 
> 8e69b1e8465711837151725c8f70e7b4b16a368e..20ade6b0558b016b581078f5cf7377e7e7c57f8e
>  100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
> @@ -21,6 +21,7 @@ static const char * const a6xx_hfi_msg_id[] = {
>       HFI_MSG_ID(HFI_H2F_MSG_PERF_TABLE),
>       HFI_MSG_ID(HFI_H2F_MSG_TEST),
>       HFI_MSG_ID(HFI_H2F_MSG_START),
> +     HFI_MSG_ID(HFI_H2F_FEATURE_CTRL),
>       HFI_MSG_ID(HFI_H2F_MSG_CORE_FW_START),
>       HFI_MSG_ID(HFI_H2F_MSG_GX_BW_PERF_VOTE),
>       HFI_MSG_ID(HFI_H2F_MSG_PREPARE_SLUMBER),
> @@ -765,23 +766,39 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
>               NULL, 0);
>  }
>  
> +static int a6xx_hfi_feature_ctrl_msg(struct a6xx_gmu *gmu, u32 feature, u32 
> enable, u32 data)
> +{
> +     struct a6xx_hfi_msg_feature_ctrl msg = {
> +             .feature = feature,
> +             .enable = enable,
> +             .data = data,
> +     };
> +
> +     return a6xx_hfi_send_msg(gmu, HFI_H2F_FEATURE_CTRL, &msg, sizeof(msg), 
> NULL, 0);
> +}
> +
> +#define HFI_FEATURE_IFPC 9

Can we please have an enum or at least a set of defines rather than
havign them scattered through the code?

> +
> +static int a6xx_hfi_enable_ifpc(struct a6xx_gmu *gmu)
> +{
> +     if (gmu->idle_level != GMU_IDLE_STATE_IFPC)
> +             return 0;
> +
> +     return a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_IFPC, 1, 0x1680);

magic number?

> +}
> +
>  #define HFI_FEATURE_ACD 12
>  
>  static int a6xx_hfi_enable_acd(struct a6xx_gmu *gmu)
>  {
>       struct a6xx_hfi_acd_table *acd_table = &gmu->acd_table;
> -     struct a6xx_hfi_msg_feature_ctrl msg = {
> -             .feature = HFI_FEATURE_ACD,
> -             .enable = 1,
> -             .data = 0,
> -     };
>       int ret;
>  
>       if (!acd_table->enable_by_level)
>               return 0;
>  
>       /* Enable ACD feature at GMU */
> -     ret = a6xx_hfi_send_msg(gmu, HFI_H2F_FEATURE_CTRL, &msg, sizeof(msg), 
> NULL, 0);
> +     ret = a6xx_hfi_feature_ctrl_msg(gmu, HFI_FEATURE_ACD, 1, 0);
>       if (ret) {
>               DRM_DEV_ERROR(gmu->dev, "Unable to enable ACD (%d)\n", ret);
>               return ret;
> @@ -898,6 +915,10 @@ int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state)
>       if (ret)
>               return ret;
>  
> +     ret = a6xx_hfi_enable_ifpc(gmu);
> +     if (ret)
> +             return ret;
> +
>       ret = a6xx_hfi_send_core_fw_start(gmu);
>       if (ret)
>               return ret;
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h 
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 
> bc063594a359ee6b796381c5fd2c30e2aa12a26d..1135beafac464f3162a3a61938a7de0c7920455a
>  100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -58,6 +58,7 @@ enum adreno_family {
>  #define ADRENO_QUIRK_HAS_CACHED_COHERENT     BIT(4)
>  #define ADRENO_QUIRK_PREEMPTION                      BIT(5)
>  #define ADRENO_QUIRK_4GB_VA                  BIT(6)
> +#define ADRENO_QUIRK_IFPC                    BIT(7)
>  
>  /* Helper for formating the chip_id in the way that userspace tools like
>   * crashdec expect.
> 
> -- 
> 2.50.1
> 

-- 
With best wishes
Dmitry

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