On Sun, Jul 20, 2025 at 05:46:14PM +0530, Akhil P Oommen wrote:
> From the hangcheck handler, KMD checks a few registers in GX
> domain to see if the GPU made any progress. But it cannot access
> those registers when IFPC is enabled. Since HW based hang detection
> is pretty decent, lets rely on it instead of these registers when
> IFPC is enabled.
>
> Signed-off-by: Akhil P Oommen <akhi...@oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 ++++++++++++--
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index
> e331cbdb117df6cfa8ae0e4c44a5aa91ba93f8eb..b3becb230a94163cccff4eaffb8eed44f1c29ad0
> 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -2399,13 +2399,23 @@ static uint32_t a6xx_get_rptr(struct msm_gpu *gpu,
> struct msm_ringbuffer *ring)
>
> static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
> {
> - struct msm_cp_state cp_state = {
> + struct msm_cp_state cp_state;
> + bool progress;
> +
> + /*
> + * With IFPC, KMD doesn't know whether GX power domain is collapsed or
> not. So, we can't
> + * blindly read the below registers in GX domain. Lets trust the hang
> detection in HW and
> + * lie to the caller that there was progress.
I know that we've relaxed code line width to 100 chars. Would it be
possible to reformat the comment to 72-75 chars?
> + */
> + if (to_adreno_gpu(gpu)->info->quirks & ADRENO_QUIRK_IFPC)
> + return true;
> +
> + cp_state = (struct msm_cp_state) {
> .ib1_base = gpu_read64(gpu, REG_A6XX_CP_IB1_BASE),
> .ib2_base = gpu_read64(gpu, REG_A6XX_CP_IB2_BASE),
> .ib1_rem = gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),
> .ib2_rem = gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE),
> };
> - bool progress;
>
> /*
> * Adjust the remaining data to account for what has already been
>
> --
> 2.50.1
>
--
With best wishes
Dmitry
