On Mon, Jul 28, 2025 at 04:28:27PM +0800, Andy Yan wrote: > From: Andy Yan <[email protected]> > > The DW DP TX Controller is compliant with the DisplayPort Specification > Version 1.4 with the following features: > > * DisplayPort 1.4a > * Main Link: 1/2/4 lanes > * Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps > * AUX channel 1Mbps > * Single Stream Transport(SST) > * Multistream Transport (MST) > * Type-C support (alternate mode) > * HDCP 2.2, HDCP 1.3 > * Supports up to 8/10 bits per color component > * Supports RBG, YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0 > * Pixel clock up to 594MHz > * I2S, SPDIF audio interface > > Add library with common helpers to make it can be shared with > other SoC. > > Signed-off-by: Andy Yan <[email protected]> > > --- > > Changes in v6: > - Use drm_dp_vsc_sdp_supported > - Store bpc/bpp/color format in dw_dp_bridge_state > > Changes in v5: > - Use drm_dp_read_sink_count_cap instead of the private implementation. > > Changes in v4: > - Drop unnecessary header files > - Switch to devm_drm_bridge_alloc > > Changes in v3: > - Rebase on drm-misc-next > - Switch to common helpers to power up/down dp link > - Only pass parameters to phy that should be set > > Changes in v2: > - Fix compile error when build as module > - Add phy init > - Only use one dw_dp_link_train_set > - inline dw_dp_phy_update_vs_emph > - Use dp_sdp > - Check return value of drm_modeset_lock > - Merge code in atomic_pre_enable/mode_fixup to atomic_check > - Return NULL if can't find a supported output format > - Fix max_link_rate from plat_data > > drivers/gpu/drm/bridge/synopsys/Kconfig | 7 + > drivers/gpu/drm/bridge/synopsys/Makefile | 1 + > drivers/gpu/drm/bridge/synopsys/dw-dp.c | 2094 ++++++++++++++++++++++ > include/drm/bridge/dw_dp.h | 20 + > 4 files changed, 2122 insertions(+) > create mode 100644 drivers/gpu/drm/bridge/synopsys/dw-dp.c > create mode 100644 include/drm/bridge/dw_dp.h >
Reviewed-by: Dmitry Baryshkov <[email protected]> -- With best wishes Dmitry
