Hi, On Mon, Jul 28, 2025 at 04:28:33PM +0800, Andy Yan wrote: > From: Andy Yan <andy....@rock-chips.com> > > The DP1 is compliant with the DisplayPort Specification > Version 1.4, and share the USBDP combo PHY1 with USB 3.1 > HOST1 controller. > > Signed-off-by: Andy Yan <andy....@rock-chips.com> > ---
The description matches the TRM:
Reviewed-by: Sebastian Reichel <sebastian.reic...@collabora.com>
Greetings,
-- Sebastian
>
> (no changes since v1)
>
> .../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 30 +++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
> index 90414486e466f..691fe941d53a1 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
> @@ -210,6 +210,36 @@ i2s10_8ch: i2s@fde00000 {
> status = "disabled";
> };
>
> + dp1: dp@fde60000 {
> + compatible = "rockchip,rk3588-dp";
> + reg = <0x0 0xfde60000 0x0 0x4000>;
> + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cru PCLK_DP1>, <&cru CLK_AUX16M_1>,
> + <&cru CLK_DP1>, <&cru MCLK_I2S8_8CH_TX>,
> + <&cru MCLK_SPDIF5_DP1>;
> + clock-names = "apb", "aux", "hdcp", "i2s", "spdif";
> + assigned-clocks = <&cru CLK_AUX16M_1>;
> + assigned-clock-rates = <16000000>;
> + resets = <&cru SRST_DP1>;
> + phys = <&usbdp_phy1 PHY_TYPE_DP>;
> + power-domains = <&power RK3588_PD_VO0>;
> + #sound-dai-cells = <0>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dp1_in: port@0 {
> + reg = <0>;
> + };
> +
> + dp1_out: port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> hdmi1: hdmi@fdea0000 {
> compatible = "rockchip,rk3588-dw-hdmi-qp";
> reg = <0x0 0xfdea0000 0x0 0x20000>;
> --
> 2.43.0
>
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