On Sat, Sep 06, 2025 at 04:53:42PM +0300, Svyatoslav Ryhel wrote: > Document CSI HW block found in Tegra20 and Tegra30 SoC. > > Signed-off-by: Svyatoslav Ryhel <[email protected]> > --- > .../display/tegra/nvidia,tegra20-csi.yaml | 104 ++++++++++++++++ > .../display/tegra/nvidia,tegra30-csi.yaml | 115 ++++++++++++++++++ > 2 files changed, 219 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml > create mode 100644 > Documentation/devicetree/bindings/display/tegra/nvidia,tegra30-csi.yaml > > diff --git > a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml > b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml > new file mode 100644 > index 000000000000..1a2858a5893c > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml > @@ -0,0 +1,104 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra20 CSI controller > + > +maintainers: > + - Svyatoslav Ryhel <[email protected]> > + > +properties: > + compatible: > + enum: > + - nvidia,tegra20-csi > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + avdd-dsi-csi-supply: > + description: DSI/CSI power supply. Must supply 1.2 V. > + > + power-domains: > + maxItems: 1 > + > + "#nvidia,mipi-calibrate-cells": > + description: The number of cells in a MIPI calibration specifier. > + Should be 1. The single cell specifies an id of the pads that > + need to be calibrated for a given device. > + $ref: /schemas/types.yaml#/definitions/uint32 > + const: 1
This property goes in the provider. Is the parent node the provider? You don't really need any of it if it's all one block. > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > +patternProperties: > + "^channel@[0-1]$": > + type: object > + description: channel 0 represents CSI-A and 1 represents CSI-B > + additionalProperties: false > + > + properties: > + reg: > + maxItems: 1 Instead: maximum: 1 > + > + nvidia,mipi-calibrate: > + description: Should contain a phandle and a specifier specifying > + which pads are used by this DSI output and need to be > + calibrated. 0 is for CSI-A, 1 is for CSI-B, 2 is for DSI. > + $ref: /schemas/types.yaml#/definitions/phandle-array Is DSI applicable here? > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: port receiving the video stream from the sensor > + > + properties: > + endpoint: > + $ref: /schemas/media/video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: true Drop. No need unless you have some constraints like number of lanes? > + > + required: > + - data-lanes > + > + required: > + - endpoint Drop. > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: port sending the video stream to the VI > + > + required: > + - reg > + - "#address-cells" > + - "#size-cells" > + - port@0 > + - port@1 > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + - clocks > + - power-domains > + - "#address-cells" > + - "#size-cells" > + > +# see nvidia,tegra20-vi.yaml for an example > diff --git > a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra30-csi.yaml > b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra30-csi.yaml > new file mode 100644 > index 000000000000..ea5ebd2f3c65 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra30-csi.yaml > @@ -0,0 +1,115 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra30-csi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra30 CSI controller > + > +maintainers: > + - Svyatoslav Ryhel <[email protected]> > + > +properties: > + compatible: > + enum: > + - nvidia,tegra30-csi > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: module clock > + - description: PAD A clock > + - description: PAD B clock > + > + clock-names: > + items: > + - const: csi > + - const: csia-pad > + - const: csib-pad Looks like clocks are the only difference? I think these 2 schemas can be merged. > + > + avdd-dsi-csi-supply: > + description: DSI/CSI power supply. Must supply 1.2 V. > + > + power-domains: > + maxItems: 1 > + > + "#nvidia,mipi-calibrate-cells": > + description: The number of cells in a MIPI calibration specifier. > + Should be 1. The single cell specifies an id of the pads that > + need to be calibrated for a given device. > + $ref: /schemas/types.yaml#/definitions/uint32 > + const: 1 > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > +patternProperties: > + "^channel@[0-1]$": > + type: object > + description: channel 0 represents CSI-A and 1 represents CSI-B > + additionalProperties: false > + > + properties: > + reg: > + maxItems: 1 > + > + nvidia,mipi-calibrate: > + description: Should contain a phandle and a specifier specifying > + which pads are used by this DSI output and need to be > + calibrated. 0 is for CSI-A, 1 is for CSI-B, 2 is for DSI-A and > + 3 is for DSI-B > + $ref: /schemas/types.yaml#/definitions/phandle-array > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 0 > + > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: port receiving the video stream from the sensor > + > + properties: > + endpoint: > + $ref: /schemas/media/video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: true > + > + required: > + - data-lanes > + > + required: > + - endpoint > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: port sending the video stream to the VI > + > + required: > + - reg > + - "#address-cells" > + - "#size-cells" > + - port@0 > + - port@1 > + > +additionalProperties: false > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - power-domains > + - "#address-cells" > + - "#size-cells" > + > +# see nvidia,tegra20-vi.yaml for an example > -- > 2.48.1 >
