From: Dongjin Kim <[email protected]> Add support for Quad HD (QHD) 2560x1440 resolution output. Timings have been adapted from the vendor kernel.
Signed-off-by: Dongjin Kim <[email protected]> Signed-off-by: Christian Hewitt <[email protected]> --- drivers/gpu/drm/meson/meson_vclk.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c index dfe0c28a0f05..f5385b3e3796 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -357,6 +357,8 @@ enum { MESON_VCLK_HDMI_594000, /* 2970 /1 /1 /1 /5 /1 => /1 /2 */ MESON_VCLK_HDMI_594000_YUV420, +/* 4830 /2 /1 /2 /5 /1 => /1 /1 */ + MESON_VCLK_HDMI_241500, }; struct meson_vclk_params { @@ -467,6 +469,18 @@ struct meson_vclk_params { .vid_pll_div = VID_PLL_DIV_5, .vclk_div = 1, }, + [MESON_VCLK_HDMI_241500] = { + .pll_freq = 4830000000, + .phy_freq = 2415000000, + .venc_freq = 241500000, + .vclk_freq = 241500000, + .pixel_freq = 241500000, + .pll_od1 = 2, + .pll_od2 = 1, + .pll_od3 = 2, + .vid_pll_div = VID_PLL_DIV_5, + .vclk_div = 1, + }, { /* sentinel */ }, }; @@ -894,6 +908,10 @@ static void meson_vclk_set(struct meson_drm *priv, m = 0xf7; frac = vic_alternate_clock ? 0x8148 : 0x10000; break; + case 4830000: + m = 0xc9; + frac = 0xd560; + break; } meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3); -- 2.34.1
