On 1/4/26 2:44 PM, Ayushi Makhija wrote:
> Add device tree nodes for the DSI0 controller with their corresponding
> PHY found on Qualcomm QCS8300 SoC.
>
> Signed-off-by: Ayushi Makhija <[email protected]>
> Reviewed-by: Dmitry Baryshkov <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/monaco.dtsi | 102 ++++++++++++++++++++++++++-
> 1 file changed, 101 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi
> b/arch/arm64/boot/dts/qcom/monaco.dtsi
> index e44fd5c33816..052ccfa6a147 100644
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -3,6 +3,7 @@
> * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> +#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
> #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/clock/qcom,sa8775p-camcc.h>
> @@ -4858,9 +4859,18 @@ port@0 {
> reg = <0>;
>
> dpu_intf0_out: endpoint {
> +
> remote-endpoint =
> <&mdss_dp0_in>;
> };
> };
> +
> + port@1 {
> + reg = <1>;
> + dpu_intf1_out: endpoint {
A newline preceding a subnode definition would be neat (and matching
the existing context visible above..)
[...]
> + port@0 {
> + reg = <0>;
> + mdss_dsi0_in: endpoint {
> +
> + remote-endpoint =
> <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + mdss_dsi0_out: endpoint {
> + };
> + };
Also in these 2 cases
In case you're going to send a v6, please take that into
consideration.
Konrad
