Hi Krzysztof, Thanks for your review! On Sun, Nov 30, 2025 at 09:24:57AM +0100, Krzysztof Kozlowski wrote: > On 26/11/2025 15:07, Tommaso Merciai wrote: > > The MIPI DSI interface on the RZ/G3E SoC is nearly identical to that of > > the RZ/V2H(P) SoC, except that this have 2 input port and can use vclk1 > > or vclk2 as DSI Video clock, depending on the selected port. > > > > To accommodate these differences, a SoC-specific > > `renesas,r9a09g047-mipi-dsi` compatible string has been added for the > > RZ/G3E SoC. > > > > Signed-off-by: Tommaso Merciai <[email protected]> > > --- > > .../bindings/display/bridge/renesas,dsi.yaml | 120 +++++++++++++++--- > > 1 file changed, 101 insertions(+), 19 deletions(-) > > > > diff --git > > a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > > b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > > index c20625b8425e..9917b494a9c9 100644 > > --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > > @@ -28,6 +28,7 @@ properties: > > - const: renesas,r9a09g057-mipi-dsi > > > > - enum: > > + - renesas,r9a09g047-mipi-dsi # RZ/G3E > > - renesas,r9a09g057-mipi-dsi # RZ/V2H(P) > > > > reg: > > @@ -84,6 +85,13 @@ properties: > > - const: pclk > > - const: vclk > > - const: lpclk > > + - items: > > + - const: pllrefclk > > + - const: aclk > > + - const: pclk > > + - const: vclk1 > > + - const: vclk2 > > + - const: lpclk > > Why are you creating completely new lists every time? > > No, come with unified approach.
The intent is not to create a completely new clock list per IP, but to keep a unified clock definition that can scale with feature differences. The previous IP supports a single DSI input port, whereas this IP supports two DSI input ports. Because of this added capability, the hardware naturally introduced an additional clock. Can you please suggest how to handle it? Kind Regards, Tommaso > > Best regards, > Krzysztof
