Hi Tommaso,
On Mon, 12 Jan 2026 at 13:00, Tommaso Merciai
<[email protected]> wrote:
> On Mon, Jan 12, 2026 at 12:35:15PM +0100, Geert Uytterhoeven wrote:
> > On Mon, 12 Jan 2026 at 12:18, Tommaso Merciai
> > <[email protected]> wrote:
> > > On Fri, Jan 09, 2026 at 06:59:12PM +0100, Geert Uytterhoeven wrote:
> > > > On Fri, 9 Jan 2026 at 18:36, Tommaso Merciai
> > > > <[email protected]> wrote:
> > > > > On Fri, Jan 09, 2026 at 05:22:02PM +0100, Geert Uytterhoeven wrote:
> > > > > > On Fri, 9 Jan 2026 at 17:06, Tommaso Merciai
> > > > > > <[email protected]> wrote:
> > > > > > > On Sun, Nov 30, 2025 at 09:24:57AM +0100, Krzysztof Kozlowski
> > > > > > > wrote:
> > > > > > > > On 26/11/2025 15:07, Tommaso Merciai wrote:
> > > > > > > > > The MIPI DSI interface on the RZ/G3E SoC is nearly identical
> > > > > > > > > to that of
> > > > > > > > > the RZ/V2H(P) SoC, except that this have 2 input port and can
> > > > > > > > > use vclk1
> > > > > > > > > or vclk2 as DSI Video clock, depending on the selected port.
> > > > > > > > >
> > > > > > > > > To accommodate these differences, a SoC-specific
> > > > > > > > > `renesas,r9a09g047-mipi-dsi` compatible string has been added
> > > > > > > > > for the
> > > > > > > > > RZ/G3E SoC.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Tommaso Merciai
> > > > > > > > > <[email protected]>
> >
> > > > > > > > > ---
> > > > > > > > > a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> > > > > > > > > +++
> > > > > > > > > b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> > > > > > > > > @@ -28,6 +28,7 @@ properties:
> > > > > > > > > - const: renesas,r9a09g057-mipi-dsi
> > > > > > > > >
> > > > > > > > > - enum:
> > > > > > > > > + - renesas,r9a09g047-mipi-dsi # RZ/G3E
> > > > > > > > > - renesas,r9a09g057-mipi-dsi # RZ/V2H(P)
> > > > > > > > >
> > > > > > > > > reg:
> > > > > > > > > @@ -84,6 +85,13 @@ properties:
> > > > > > > > > - const: pclk
> > > > > > > > > - const: vclk
> > > > > > > > > - const: lpclk
> > > > > > > > > + - items:
> > > > > > > > > + - const: pllrefclk
> > > > > > > > > + - const: aclk
> > > > > > > > > + - const: pclk
> > > > > > > > > + - const: vclk1
> > > > > > > > > + - const: vclk2
> > > > > > > > > + - const: lpclk
> > > > > > > >
> > > > > > > > Why are you creating completely new lists every time?
> > > > > > > >
> > > > > > > > No, come with unified approach.
> > > > > > >
> > > > > > > The intent is not to create a completely new clock list per IP,
> > > > > > > but to keep a
> > > > > > > unified clock definition that can scale with feature differences.
> > > > > > >
> > > > > > > The previous IP supports a single DSI input port, whereas this IP
> > > > > > > supports two
> > > > > > > DSI input ports.
> > > > > > >
> > > > > > > Because of this added capability, the hardware naturally
> > > > > > > introduced an
> > > > > > > additional clock.
> > > > > > >
> > > > > > > Can you please suggest how to handle it?
> > > > > >
> > > > > > Keep on calling the first vclk "vclk", and add "vclk2" at the end
> > > > > > of the list?
> > > > > > Then RZ/V2H can specify the first 5 clocks, and RZ/G3E can specify
> > > > > > all 6.
> > > > >
> > > > > Testing a bit your suggestion
> > > > > we can do:
> > > > >
> > > > > clock-names:
> > > > > oneOf:
> > > > > - items:
> > > > > - const: pllclk
> > > > > - const: sysclk
> > > > > - const: aclk
> > > > > - const: pclk
> > > > > - const: vclk
> > > > > - const: lpclk
> > > > > - minItems: 5
> > > > > items:
> > > > > - const: pllrefclk
> > > > > - const: aclk
> > > > > - const: pclk
> > > > > - const: vclk
> > > > > - const: lpclk
> > > > > - const: vclk2
> > > > >
> > > > > Then later into the compatible if switch we can do:
> > > > >
> > > > >
> > > > > - if:
> > > > > properties:
> > > > > compatible:
> > > > > contains:
> > > > > const: renesas,r9a09g047-mipi-dsi
> > > > > then:
> > > > > properties:
> > > > > clocks:
> > > > > items:
> > > > > - description: DSI PLL reference input clock
> > > > > - description: DSI AXI bus clock
> > > > > - description: DSI Register access clock
> > > > > - description: DSI Video clock
> > > > > - description: DSI D-PHY Escape mode transmit clock
> > > > > - description: DSI Video clock (2nd input clock)
> > > >
> > > > All descriptions belong at the top level. Just add the 6th one.
> > >
> > > Please correct me if I'm wrong but if we move up:
> > >
> > > - description: DSI Video clock (2nd input clock)
> > >
> > > To the top level description we will have 6 clocks for G3E and 6 for
> > > RZ/G2L. With that I think dt_binding_check will fail ("is valid under
> > > each of") because of the oneOf.
> >
> > RZ/G2L and RZ/V2H need "maxItems: 5" in their if-sections.
>
> RZ/V2H -> maxItems: 5 is fine.
> RZ/G2L -> needs 6 clocks no?
>
> Please correct me if I'm wrong.
Sorry, RZ/G2L indeed has 6 clocks, as it has sysclk.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
