Hi Tommaso,
On Wed, 26 Nov 2025 at 15:08, Tommaso Merciai
<[email protected]> wrote:
> Add PLLDSI clk mux support to select PLLDSI clock from different clock
> sources.
>
> Introduce the DEF_PLLDSI_SMUX() macro to define these muxes and register
> them in the clock driver.
>
> Extend the determine_rate callback to calculate and propagate PLL
> parameters via rzv2h_get_pll_dtable_pars() when LVDS output is selected,
> using a new helper function rzv2h_cpg_plldsi_smux_lvds_determine_rate().
>
> Signed-off-by: Tommaso Merciai <[email protected]>
Thanks for your patch!
> --- a/drivers/clk/renesas/rzv2h-cpg.c
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> +
> +static int rzv2h_cpg_plldsi_smux_lvds_determine_rate(struct rzv2h_cpg_priv
> *priv,
> + struct pll_clk *pll_clk,
> + struct clk_rate_request
> *req)
> +{
> + struct rzv2h_pll_div_pars *dsi_params;
> + struct rzv2h_pll_dsi_info *dsi_info;
> + u8 lvds_table[] = { 7 };
> + u64 rate_millihz;
> +
> + dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];
> + dsi_params = &dsi_info->pll_dsi_parameters;
> +
> + rate_millihz = mul_u32_u32(req->rate, MILLI);
> + if (!rzv2h_get_pll_divs_pars(dsi_info->pll_dsi_limits, dsi_params,
> + lvds_table, 1, rate_millihz)) {
s/1/ARRAY_SIZE(lvds_table)/
> + dev_err(priv->dev, "failed to determine rate for req->rate:
> %lu\n",
> + req->rate);
> + return -EINVAL;
> + }
> +
> + req->rate = DIV_ROUND_CLOSEST_ULL(dsi_params->div.freq_millihz,
> MILLI);
> + req->best_parent_rate = req->rate;
> + dsi_info->req_pll_dsi_rate = req->best_parent_rate *
> dsi_params->div.divider_value;
> +
> + return 0;
> +}
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
