Hi Tommaso,
On Mon, 12 Jan 2026 at 09:13, Tommaso Merciai
<[email protected]> wrote:
> On Fri, Jan 09, 2026 at 07:27:04PM +0100, Geert Uytterhoeven wrote:
> > On Wed, 26 Nov 2025 at 15:08, Tommaso Merciai
> > <[email protected]> wrote:
> > > Add PLLDSI clk mux support to select PLLDSI clock from different clock
> > > sources.
> > >
> > > Introduce the DEF_PLLDSI_SMUX() macro to define these muxes and register
> > > them in the clock driver.
> > >
> > > Extend the determine_rate callback to calculate and propagate PLL
> > > parameters via rzv2h_get_pll_dtable_pars() when LVDS output is selected,
> > > using a new helper function rzv2h_cpg_plldsi_smux_lvds_determine_rate().
> > >
> > > Signed-off-by: Tommaso Merciai <[email protected]>
> >
> > Thanks for your patch!
> >
> > > --- a/drivers/clk/renesas/rzv2h-cpg.c
> > > +++ b/drivers/clk/renesas/rzv2h-cpg.c
> >
> > [...]
> >
> > > static int rzv2h_cpg_pll_clk_is_enabled(struct clk_hw *hw)
> > > {
> > > struct pll_clk *pll_clk = to_pll(hw);
> > > @@ -1085,6 +1213,9 @@ rzv2h_cpg_register_core_clk(const struct
> > > cpg_core_clk *core,
> > > case CLK_TYPE_PLLDSI_DIV:
> > > clk = rzv2h_cpg_plldsi_div_clk_register(core, priv);
> > > break;
> > > + case CLK_TYPE_PLLDSI_SMUX:
> > > + clk = rzv2h_cpg_plldsi_smux_clk_register(core, priv);
> > > + break;
> > > default:
> > > goto fail;
> > > }
> > > diff --git a/drivers/clk/renesas/rzv2h-cpg.h
> > > b/drivers/clk/renesas/rzv2h-cpg.h
> > > index dc957bdaf5e9..5f6e775612e7 100644
> > > --- a/drivers/clk/renesas/rzv2h-cpg.h
> > > +++ b/drivers/clk/renesas/rzv2h-cpg.h
> > > @@ -203,6 +203,7 @@ enum clk_types {
> > > CLK_TYPE_SMUX, /* Static Mux */
> > > CLK_TYPE_PLLDSI, /* PLLDSI */
> > > CLK_TYPE_PLLDSI_DIV, /* PLLDSI divider */
> > > + CLK_TYPE_PLLDSI_SMUX, /* PLLDSI Static Mux */
> > > };
> > >
> > > #define DEF_TYPE(_name, _id, _type...) \
> > > @@ -241,6 +242,13 @@ enum clk_types {
> > > .dtable = _dtable, \
> > > .parent = _parent, \
> > > .flag = CLK_SET_RATE_PARENT)
> > > +#define DEF_PLLDSI_SMUX(_name, _id, _smux_packed, _parent_names) \
> > > + DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI_SMUX, \
> > > + .cfg.smux = _smux_packed, \
> > > + .parent_names = _parent_names, \
> > > + .num_parents = ARRAY_SIZE(_parent_names), \
> > > + .flag = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, \
> > > + .mux_flags = CLK_MUX_HIWORD_MASK)
> > >
> > > /**
> > > * struct rzv2h_mod_clk - Module Clocks definitions
> >
> > Why do you need a completely new clock type, and can't you just use
> > the existing CLK_TYPE_SMUX?
>
> From reference manual (Table 4.4-10 Specifications of the CPG_SSELm
> Registers)
>
> We have the following:
>
> - SMUX2_DSI0_CLK*2
> 0b: CDIV7_DSI0_CLK (default)
> 1b: CSDIV_2to16_PLLDSI0
>
> - SMUX2_DSI1_CLK*2
> 0b: CDIV7_DSI1_CLK (default)
> 1b: CSDIV_2to16_PLLDSI1
>
> Note 2.If LVDS0 / LVDS1 is used, be sure to set 0b.
>
> For this reason these clocks needs an ad hoc determine_rate function:
> - rzv2h_cpg_plldsi_smux_determine_rate()
>
> For that CLK_TYPE_PLLDSI_SMUX has been introduced.
> What do you think?
OK, your solution sounds good to me. Still, as this is used from the
DRM driver, I would like to get some feedback from the DRM people, too.
BTW, I just noticed in the RZ/G3E clock system diagram that
CDIV7_DSI0_CLK has a duty cycle "DUTY H/L=4/3", while all other clocks
use the symmetrical 50%. Perhaps the DRM driver can request a duty
cycle of 4/7 when using LVDS? Currently the DRM driver communicates
its requirements by explicitly setting the parent.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
