On Thu, Jan 15, 2026 at 12:21:51AM +0100, Danilo Krummrich wrote:
> (Cc: Zhi, Matt, Alex)
>
> On Tue Dec 2, 2025 at 11:03 PM CET, Lyude Paul wrote:
> > This introduces a set of bindings for working with iosys_map in rust code.
> > The design of this is heavily based off the design for both the io and
> > dma_map bindings for Rust.
>
> I already had a chat with Lyude about this, but also want to post it here. I
> have mainly two comment on this:
>
> (1) The backing memory of iosys_map may be a device resource and hence has
> to
> be protected against (bus) device / driver unbind.
>
> (2) The idea for the generic I/O infrastructure is to support arbitrary I/O
> backends rather than only MMIO. For instance, this can also be PCI
> configuration space, I2C, SPI, etc., but also DMA, VRAM, system memory,
> etc.
>
> For this, there is a patch series from Zhi [1] splitting up the current
> I/O structures into traits that we will land soon.
>
> We will also have macros analogous to dma_read!() and dma_write!() for
> the
> generic I/O infrastructure, which Matt also works on for his QC SoC
> driver.
>
> This will allow us to unify all kinds of I/O operations into a single
> interface, supporting the read!() and write!() accessors for values, the
> register!() macro and raw accessors, such as e.g. read32().
>
> With this we will have something that is way more powerful than
> iosys_map
> and makes this abstraction obsolete.
The trait approach generally requires knowing the target type at
compile-time or paying dynamic function calls, but my understanding is
that iosys exists because you might not know which variant you want at
compile-time.
Perhaps we need an
enum Iosys {
SystemMemory(...),
DmaMemory(...),
}
and implement Io for Iosys in terms of the inner types.
Alice
