On Fri, 16 Jan 2026 12:37:39 +0800, Icenowy Zheng wrote: > From: Icenowy Zheng <[email protected]> > > Verisilicon has a series of display controllers prefixed with DC and > with self-identification facility like their GC series GPUs. > > Add a device tree binding for it. > > Depends on the specific DC model, it can have either one or two display > outputs, and each display output could be set to DPI signal or "DP" > signal (which seems to be some plain parallel bus to HDMI controllers). > > Signed-off-by: Icenowy Zheng <[email protected]> > Signed-off-by: Icenowy Zheng <[email protected]> > --- > Changes in v5: > - Dropped the requirement of port@0. > - Dropped the if clause for TH1520, which seems to be not needed because > of implicit DT binding rules. > > Changes in v4: > - Added a comment for "verisilicon,dc" that says the ID/revision is > discoverable via registers. > - Removed clock minItems constraint w/o specific compatible strings. > > Changes in v3: > - Added SoC-specific compatible string, and arm the binding with clock / > port checking for the specific SoC (with a 2-output DC). > > Changes in v2: > - Fixed misspelt "versilicon" in title. > - Moved minItems in clock properties to be earlier than items. > - Re-aligned multi-line clocks and resets in example. > > .../bindings/display/verisilicon,dc.yaml | 122 ++++++++++++++++++ > 1 file changed, 122 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/verisilicon,dc.yaml >
Reviewed-by: Rob Herring (Arm) <[email protected]>
