On Monday 18 June 2001 13:00, you wrote:
> I'm also starting to look at the code for the mach64. What do you mean with
> the new driver template code? Are you talking about the structure of the
> ATI driver in the mach64 branch?
I think that's what the code that's in the trunk is using for design
internals.
For what it's worth, I've been trying to kick-start drivers for a little
while now (My free time got cut a little short with a search for a new job
necessitated by a surprise mass-layoff at my previous employer and other
minor annoyances like that). I'd say that while the Mach64 code in the
archives is a good crib sheet, but I don't know if it'd be good for moving
into production use (I'm sure that Gareth, if he's still listening in, might
offer an opinion in that regard...)- it might be better if one of us started
from ground zero with the driver since much has changed since the code was
last touched by Gareth.
I'm getting back up to speed free-time-wise and I'm eyeing the the prospects
of starting fresh with this driver. One of the things you need to be aware
of with the RagePRO and it's ilk is how the bus mastering works- it's a
strange animal to say the least.
RagePRO bus mastering is a scatter-gather system that works from PCI memory
space to the card's memory map. It transfers memory in blocks of 4k or less
described in a table that is handed to the card. This descriptor table can
be any size up to 64 or 128k (can't remember exactly and I'm at work right
now so I can't look at my reference books...) in increments of 16k. The
descriptor table _must_ be aligned on a boundary matching the size you
specify for the table- 16k on a 16 boundary, etc.
--
Frank Earl
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