On Wed, 2002-04-24 at 16:49, Frank C.Earl wrote:
> On Wednesday 24 April 2002 06:15 am, you wrote:
> 
> Hi, there!
> 
> > For enabling DMA on Mach64 I'll need to allocate two extra DMA buffers: a
> > primary DMA buffer and a decription table buffer.
> 
> All you need for now is a descriptor table.  The buffers that you have 
> already allocated via the DRM's framework should be allocated page aligned 
> and you'll have the bus address in hand.  The only reason you'd need a 
> "primary" buffer is if you had an engine that wasn't at all secure.

Regardless of security concerns, the idea was to use this primary buffer
for storing the state update emitted from the DRM. The first entry of
the descriptor table would point to this primary buffer, and the
followings to the client submitted buffer. Anyway, I agree that for the
time being this can stay as MMIO.

> ....  For now, I'd be seeing 
> what you can do to just get it going. All you need is a descriptor table at 
> that point.  Use the memory pool api to allocate that one just like in the 
> BUS-Master test.

Initially I thought of this too, but since the amount of changes would
be almost the same I preferred to investigate a little further how to do
it definitively.

> At that point, we'll have a DMA system (Though it ties up 
> the framework for any given pass- the code I'm completing happens to have a 
> full-blown queue, etc that is governed by the CTRC interrupt.). It may not 
> be quite what I have in hand, but as Gareth has said before, get it working- 

Do you think that the interrupt is necessary? Wouldn't it be possible to
use a scratch register for doing buffer aging as it's done in the other
cards?

> I'm just waay to busy to have completed what I had in mind up until recently. 

Could you share with us what you had in mind before? Now that Leif and I
have been studying a little this subject I think we are able to follow
and discuss your ideas.

> 
> -- 
> Frank Earl
> 

Regards,

Jose Fonseca



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