On Wed, 1 May 2002, José Fonseca wrote: > > > > > ... or we > > > bring Frank's changes to mach64-0-0-4-branch. Personally I'm more in > > favor > > > of the later, since it will avoid redundant work of merging back and > > > forward, and will also enable the PowerPC architecture to participate > > > in testing. > > > > I'm for it, ... > > Great. So we are all in agreement in this matter. >
I wanted to give you an update on my progress since I sent the first patch of my merge. None of this is checked in yet, btw. I added the necessary initialization to atidri.c, based on the glint/gamma driver, and got the interrupt service routine successfully installed and handling VBLANK interrupts. That was just a matter of getting the IRQ number through a DRM function and calling the control ioctl as part of the DRI screen init. However, when exiting the X server, I get a hard lockup. I haven't found the source of the problem yet. I filled in the DRIVER_[PRE,POST,UN]INSTALL macros in mach64.h to disable/enable interrupts in CRTC_INT_CNTL, and the PRE/POST work, but the UNINSTALL isn't even reached before the lockup as far as I can tell. These macros are called from the template code in _irq_install/_irq_uninstall. There seem to be some discrepencies in the docs concerning FIFO and HOST error interrupts. First off, I don't see any bits to enable these interrupts listed in BUS_CNTL. Second, the sample code uses 0x00a00000 in the engine reset function to clear/acknowledge these error conditions (this is in our current rest function as well). However, these bits are listed in the docs as something unrelated. The lower bit -- which is used in Frank's code to ack a host error (the comment says this is per Vernon Chiang at ATI) -- is always set by default on my card. That meant that the first time I got the code running, it was resetting the engine on every VBLANK! This needs some more investigation and maybe another email to ATI. I started filling in the dma_dispatch from the code already in _dispatch_vertex, and realized that we'll need to factor in special handling for dispatching blits, since these work differently from GUI-master operations. We could use the HOST_DATA registers and treat blits as GUI masters as the utah driver does, but then you don't get an interrupt on completion. The last thing is that I also started looking at how to initialize the freelist and hand out buffers. I haven't done a thorough comparison, but I was wondering if we could use the freelist/waitlist/queue code in the DRM templates. They include spinlocks for manipulating list pointers and other details I haven't had the time to fully understand yet, but I think gamma and i830 use them. Now, it's time for sleep... -- Leif Delgass http://www.retinalburn.net _______________________________________________________________ Have big pipes? SourceForge.net is looking for download mirrors. We supply the hardware. You get the recognition. Email Us: [EMAIL PROTECTED] _______________________________________________ Dri-devel mailing list [EMAIL PROTECTED] https://lists.sourceforge.net/lists/listinfo/dri-devel
