On Thu, 2002-05-30 at 15:27, Keith Whitwell wrote:
> Michel Dänzer wrote:
> > On Thu, 2002-05-30 at 11:24, Keith Whitwell wrote:
> > 
> >>>I conclude from this that writing the ring tail register causes the card to 
> >>>fetch all the commands up until that point and feed them to its FIFO, which 
> >>>may fill it... It's certainly possible for the FIFO to go from 64 slots 
> >>>free to 0 in one ioctl...
> >>>
> >>>...so maybe what we need is some clue as to exactly how many commands we're 
> >>>about to feed it (I made Wild-Ass-Guesses about the number of commands when 
> >>>we were just blasting a buffer from userspace, which may go a long way to 
> >>>explaining the sucky performance), and then something to make a prediction 
> >>>on how long it'll take the card to clear the FIFO based on current 
> >>>performance (constantly hammering on the status register is probably not a 
> >>>good way of doing this :-)
> >>>
> >>Maybe this side of it is true, BUT, if the path is ring->fifo, then I think we 
> >>can assume that the card knows how to wait for the fifo before feeding it the 
> >>next bit of the ring.  Otherwise, everything would crash...
> >>
> > 
> > Right, but do we check if there is room before feeding the FIFO
> > directly?
> 
> No, not from the kernel module.  I think this has to change.  But the only 
> places where we potentially do it directly are where we issue RADEON_WRITE's 
> -- I don't think we have to check just to add stuff to the ring.

Agreed. Are there direct register writes while the CP is running? If
yes, are they necessary? (I'm at work and don't have time to check
myself right now, sorry)


-- 
Earthling Michel Dänzer (MrCooper)/ Debian GNU/Linux (powerpc) developer
XFree86 and DRI project member   /  CS student, Free Software enthusiast

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