On Thursday 30 May 2002 10:24 am, Keith Whitwell scribed numinously:"
> > I conclude from this that writing the ring tail register causes the
> > card to fetch all the commands up until that point and feed them to its
> > FIFO, which may fill it... It's certainly possible for the FIFO to go
> > from 64 slots free to 0 in one ioctl...
> >
> > ...so maybe what we need is some clue as to exactly how many commands
> > we're about to feed it (I made Wild-Ass-Guesses about the number of
> > commands when we were just blasting a buffer from userspace, which may
> > go a long way to explaining the sucky performance), and then something
> > to make a prediction on how long it'll take the card to clear the FIFO
> > based on current performance (constantly hammering on the status
> > register is probably not a good way of doing this :-)
>
> Maybe this side of it is true, BUT, if the path is ring->fifo, then I
> think we can assume that the card knows how to wait for the fifo before
> feeding it the next bit of the ring.  Otherwise, everything would
> crash...

Obviously :-) Otherwise the trace in my last mail would have indicated a 
crash, but it recovered from that.

It does seem like a good idea to know how much we just gave the card to do 
though, so we have some idea to how long to wait next time we do wait.

It may be significant is that the problem I'm getting occurs the first time 
it does do_cp_idle() when the FIFO was not *already* empty. This is to say, 
if it has to wait at all, it will go all funny.

I checked out the new stuff and ran with RADEON_DEBUG_SANITY, and it didn't 
flag anything, though the fix for the tuxkart hang seems to have made the 
wireframe highlight boxes it uses to indicate the currently selected object 
spray lines randomly around the screen.

-- 
Tim Smith ([EMAIL PROTECTED])
Food for myself is one thing, but food for a whole village? That is a lot
of cheese dip.
  -- Groo the Wanderer


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