Also, Stephane has corrected the clearing problems if other windows were moved on top of a rendering window. However, for now clearing will clear all tiles up to the end of the window completely, so better don't try multiple apps or mixed hyperz/non-hyperz apps - you have been warned.
I have found no way unfortunately how to clear only the z or only the stencil buffer - the respective registers such as STENCILREFMASK and ZSTENCILCNTL do not seem to affect the hyperz clear call in any way, shape or form (and thus they are gone from the drm patch), I suspect they are only used when using the rasterizer for writing to the z/stencil buffer. This can obviously lead to rendering errors (try stencil_wrap with the attached patch to see what I mean - of course that's only useful if it ran correctly before...).
I do not know if this is a hardware limitation or not (and so far I was not succesful in getting fglrx to enable hyperz so I could measure clear speed when only clearing some buffers). If it's a hardware limitation it might be necessary to use a fallback when only stencil or z buffer are cleared (for visuals with a stencil buffer only of course).
Here is a picture of depth/stencil problems in nwn: http://homepage.hispeed.ch/rscheidegger/dri_experimental/nwn_hyperz.png - I do not really know if this is caused by this clearing problem (warning, 1MB picture), but it definitely looks like a z-buffer problem.
Stencil/Depth readback still don't work.
For owners of r200 and r100 cards, you might want to test the code path for rv cards if it doesn't work (i.e. don't set RADEON_Z_HIERARCHY_ENABLE in the dri driver, and change the CHIP_IS_RV if's in the drm accordingly), as these are better tested currently. (I used the rv path successfully on a r100 (with the tile nr of the non-rv path however), though I had lots of lockups - not sure if the lockups really were hyperz related, they might have happened just because the clear ioctl was faster, rendering was correct, q3a 40% faster when it actually managed to finish the timedemo, and full screen glxgears 90% faster.) You might also want to try increasing the nroftiles in drm (try increasing by factors of 2) or if it runs correctly, try decreasing it in the case you're actually clearing too much tiles...
Roland
Index: shared/drm_pciids.txt
===================================================================
RCS file: /cvs/dri/drm/shared/drm_pciids.txt,v
retrieving revision 1.9
diff -u -r1.9 drm_pciids.txt
--- shared/drm_pciids.txt 7 Nov 2004 02:19:58 -0000 1.9
+++ shared/drm_pciids.txt 9 Nov 2004 22:43:00 -0000
@@ -1,35 +1,35 @@
[radeon]
-0x1002 0x4136 CHIP_RS100|CHIP_IS_IGP "ATI Radeon RS100 IGP 320M"
-0x1002 0x4137 CHIP_RS200|CHIP_IS_IGP "ATI Radeon RS200 IGP"
+0x1002 0x4136 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS100 IGP 320M"
+0x1002 0x4137 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS200 IGP"
0x1002 0x4144 CHIP_R300 "ATI Radeon AD 9500 Pro"
0x1002 0x4145 CHIP_R300 "ATI Radeon AE 9700 Pro"
0x1002 0x4146 CHIP_R300 "ATI Radeon AF 9700 Pro"
0x1002 0x4147 CHIP_R300 "ATI FireGL AG Z1/X1"
-0x1002 0x4150 CHIP_RV350 "ATI Radeon AP 9600"
-0x1002 0x4151 CHIP_RV350 "ATI Radeon AQ 9600"
-0x1002 0x4152 CHIP_RV350 "ATI Radeon AR 9600"
-0x1002 0x4153 CHIP_RV350 "ATI Radeon AS 9600 AS"
-0x1002 0x4154 CHIP_RV350 "ATI FireGL AT T2"
-0x1002 0x4156 CHIP_RV350 "ATI FireGL AV T2"
-0x1002 0x4237 CHIP_RS250|CHIP_IS_IGP "ATI Radeon RS250 IGP"
+0x1002 0x4150 CHIP_RV350|CHIP_IS_RV "ATI Radeon AP 9600"
+0x1002 0x4151 CHIP_RV350|CHIP_IS_RV "ATI Radeon AQ 9600"
+0x1002 0x4152 CHIP_RV350|CHIP_IS_RV "ATI Radeon AR 9600"
+0x1002 0x4153 CHIP_RV350|CHIP_IS_RV "ATI Radeon AS 9600 AS"
+0x1002 0x4154 CHIP_RV350|CHIP_IS_RV "ATI FireGL AT T2"
+0x1002 0x4156 CHIP_RV350|CHIP_IS_RV "ATI FireGL AV T2"
+0x1002 0x4237 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS250 IGP"
0x1002 0x4242 CHIP_R200 "ATI Radeon BB R200 AIW 8500DV"
0x1002 0x4242 CHIP_R200 "ATI Radeon BC R200"
-0x1002 0x4336 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS100
Mobility U1"
-0x1002 0x4337 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS200
Mobility IGP 340M"
-0x1002 0x4437 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS250
Mobility IGP"
-0x1002 0x4964 CHIP_R250 "ATI Radeon Id R250 9000"
-0x1002 0x4965 CHIP_R250 "ATI Radeon Ie R250 9000"
-0x1002 0x4966 CHIP_R250 "ATI Radeon If R250 9000"
-0x1002 0x4967 CHIP_R250 "ATI Radeon Ig R250 9000"
+0x1002 0x4336 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon
RS100 Mobility U1"
+0x1002 0x4337 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon
RS200 Mobility IGP 340M"
+0x1002 0x4437 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon
RS250 Mobility IGP"
+0x1002 0x4964 CHIP_R250|CHIP_IS_RV "ATI Radeon Id R250 9000"
+0x1002 0x4965 CHIP_R250|CHIP_IS_RV "ATI Radeon Ie R250 9000"
+0x1002 0x4966 CHIP_R250|CHIP_IS_RV "ATI Radeon If R250 9000"
+0x1002 0x4967 CHIP_R250|CHIP_IS_RV "ATI Radeon Ig R250 9000"
0x1002 0x4C57 CHIP_RV200|CHIP_IS_MOBILITY "ATI Radeon LW RV200 Mobility 7500
M7"
0x1002 0x4C58 CHIP_RV200|CHIP_IS_MOBILITY "ATI Radeon LX RV200 Mobility FireGL
7800 M7"
-0x1002 0x4C59 CHIP_RV100|CHIP_IS_MOBILITY "ATI Radeon LY RV100 Mobility M6"
-0x1002 0x4C5A CHIP_RV100|CHIP_IS_MOBILITY "ATI Radeon LZ RV100 Mobility M6"
-0x1002 0x4C64 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Ld R250 Mobility 9000 M9"
-0x1002 0x4C65 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Le R250 Mobility 9000 M9"
-0x1002 0x4C66 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Lf R250 Mobility 9000 M9"
-0x1002 0x4C67 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Lg R250 Mobility 9000 M9"
-0x1002 0x4E50 CHIP_RV350|CHIP_IS_MOBILITY "ATI Radeon RV300 Mobility 9600 M10"
+0x1002 0x4C59 CHIP_RV100|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon LY RV100
Mobility M6"
+0x1002 0x4C5A CHIP_RV100|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon LZ RV100
Mobility M6"
+0x1002 0x4C64 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Ld R250
Mobility 9000 M9"
+0x1002 0x4C65 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Le R250
Mobility 9000 M9"
+0x1002 0x4C66 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Lf R250
Mobility 9000 M9"
+0x1002 0x4C67 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Lg R250
Mobility 9000 M9"
+0x1002 0x4E50 CHIP_RV350|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RV350
Mobility 9600 M10"
0x1002 0x5144 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QD R100"
0x1002 0x5145 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QE R100"
0x1002 0x5146 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QF R100"
@@ -44,30 +44,30 @@
0x1002 0x514F CHIP_R200 "ATI Radeon QO R200 8500 LE"
0x1002 0x5157 CHIP_RV200 "ATI Radeon QW RV200 7500"
0x1002 0x5158 CHIP_RV200 "ATI Radeon QX RV200 7500"
-0x1002 0x5159 CHIP_RV100 "ATI Radeon QY RV100 7000/VE"
-0x1002 0x515A CHIP_RV100 "ATI Radeon QZ RV100 7000/VE"
+0x1002 0x5159 CHIP_RV100|CHIP_IS_RV "ATI Radeon QY RV100 7000/VE"
+0x1002 0x515A CHIP_RV100|CHIP_IS_RV "ATI Radeon QZ RV100 7000/VE"
0x1002 0x5168 CHIP_R200 "ATI Radeon Qh R200"
0x1002 0x5169 CHIP_R200 "ATI Radeon Qi R200"
0x1002 0x516A CHIP_R200 "ATI Radeon Qj R200"
0x1002 0x516B CHIP_R200 "ATI Radeon Qk R200"
0x1002 0x516C CHIP_R200 "ATI Radeon Ql R200"
-0x1002 0x5834 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
-0x1002 0x5835 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS300
Mobility IGP"
-0x1002 0x5836 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
-0x1002 0x5837 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
-0x1002 0x5960 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5961 CHIP_RV280 "ATI Radeon RV280 9200 SE"
-0x1002 0x5962 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5963 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5964 CHIP_RV280 "ATI Radeon RV280 9200 SE"
-0x1002 0x5968 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5969 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x596A CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x596B CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5c61 CHIP_RV280|CHIP_IS_MOBILITY "ATI Radeon RV280 Mobility"
-0x1002 0x5c62 CHIP_RV280 "ATI Radeon RV280"
-0x1002 0x5c63 CHIP_RV280|CHIP_IS_MOBILITY "ATI Radeon RV280 Mobility"
-0x1002 0x5c64 CHIP_RV280 "ATI Radeon RV280"
+0x1002 0x5834 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS300 IGP"
+0x1002 0x5835 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon
RS300 Mobility IGP"
+0x1002 0x5836 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS300 IGP"
+0x1002 0x5837 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS300 IGP"
+0x1002 0x5960 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5961 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200 SE"
+0x1002 0x5962 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5963 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5964 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200 SE"
+0x1002 0x5968 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5969 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x596A CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x596B CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5c61 CHIP_RV280|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RV280
Mobility"
+0x1002 0x5c62 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280"
+0x1002 0x5c63 CHIP_RV280|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RV280
Mobility"
+0x1002 0x5c64 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280"
[r128]
0x1002 0x4c45 0 "ATI Rage 128 Mobility LE (PCI)"
Index: shared/radeon.h
===================================================================
RCS file: /cvs/dri/drm/shared/radeon.h,v
retrieving revision 1.33
diff -u -r1.33 radeon.h
--- shared/radeon.h 23 Oct 2004 06:25:56 -0000 1.33
+++ shared/radeon.h 9 Nov 2004 22:43:01 -0000
@@ -45,7 +45,7 @@
#define DRIVER_DATE "20020828"
#define DRIVER_MAJOR 1
-#define DRIVER_MINOR 12
+#define DRIVER_MINOR 13
#define DRIVER_PATCHLEVEL 0
/* Interface history:
@@ -82,6 +82,8 @@
* and GL_EXT_blend_[func|equation]_separate on r200
* 1.12- Add R300 CP microcode support - this just loads the CP on r300
* (No 3D support yet - just microcode loading).
+ * 1.13- Add packed R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
+ * - Added RADEON_CLEAR_HYPERZ flag to clear ioctl.
*/
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, \
Index: shared/radeon_drm.h
===================================================================
RCS file: /cvs/dri/drm/shared/radeon_drm.h,v
retrieving revision 1.24
diff -u -r1.24 radeon_drm.h
--- shared/radeon_drm.h 23 Oct 2004 06:25:56 -0000 1.24
+++ shared/radeon_drm.h 9 Nov 2004 22:43:01 -0000
@@ -145,7 +145,8 @@
#define RADEON_EMIT_PP_TEX_SIZE_1 74
#define RADEON_EMIT_PP_TEX_SIZE_2 75
#define R200_EMIT_RB3D_BLENDCOLOR 76
-#define RADEON_MAX_STATE_PACKETS 77
+#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
+#define RADEON_MAX_STATE_PACKETS 78
/* Commands understood by cmd_buffer ioctl. More can be added but
@@ -193,6 +194,7 @@
#define RADEON_BACK 0x2
#define RADEON_DEPTH 0x4
#define RADEON_STENCIL 0x8
+#define RADEON_CLEAR_HYPERZ 0x8000000
/* Primitive types
*/
Index: shared/radeon_drv.h
===================================================================
RCS file: /cvs/dri/drm/shared/radeon_drv.h,v
retrieving revision 1.37
diff -u -r1.37 radeon_drv.h
--- shared/radeon_drv.h 9 Nov 2004 00:54:19 -0000 1.37
+++ shared/radeon_drv.h 9 Nov 2004 22:43:02 -0000
@@ -68,6 +68,7 @@
CHIP_IS_IGP = 0x00020000UL,
CHIP_SINGLE_CRTC = 0x00040000UL,
CHIP_IS_AGP = 0x00080000UL,
+ CHIP_IS_RV = 0x00100000UL,
};
#define GET_RING_HEAD(dev_priv) DRM_READ32(
(dev_priv)->ring_rptr, 0 )
@@ -411,6 +412,7 @@
# define RADEON_STENCIL_ENABLE (1 << 7)
# define RADEON_Z_ENABLE (1 << 8)
#define RADEON_RB3D_DEPTHOFFSET 0x1c24
+#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
#define RADEON_RB3D_DEPTHPITCH 0x1c28
#define RADEON_RB3D_PLANEMASK 0x1d84
#define RADEON_RB3D_STENCILREFMASK 0x1d7c
@@ -423,11 +425,15 @@
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_Z_TEST_MASK (7 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
+# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
+# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
+# define RADEON_FORCE_Z_DIRTY (1 << 29)
# define RADEON_Z_WRITE_ENABLE (1 << 30)
+# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
@@ -535,7 +541,7 @@
# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
-#define RADEON_RB3D_ZMASKOFFSET 0x1c34
+#define RADEON_RB3D_ZMASKOFFSET 0x3234
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
@@ -590,6 +596,8 @@
# define RADEON_3D_DRAW_IMMD 0x00002900
# define RADEON_3D_DRAW_INDX 0x00002A00
# define RADEON_3D_LOAD_VBPNTR 0x00002F00
+# define RADEON_3D_CLEAR_ZMASK 0x00003200
+# define RADEON_3D_CLEAR_HIZ 0x00003700
# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
# define RADEON_CNTL_PAINT_MULTI 0x00009A00
# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
@@ -748,6 +756,8 @@
#define R200_RB3D_BLENDCOLOR 0x3218
+#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
+
/* Constants */
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
Index: shared/radeon_state.c
===================================================================
RCS file: /cvs/dri/drm/shared/radeon_state.c,v
retrieving revision 1.39
diff -u -r1.39 radeon_state.c
--- shared/radeon_state.c 23 Oct 2004 06:25:56 -0000 1.39
+++ shared/radeon_state.c 9 Nov 2004 22:43:04 -0000
@@ -205,6 +205,7 @@
case RADEON_EMIT_PP_TEX_SIZE_1:
case RADEON_EMIT_PP_TEX_SIZE_2:
case R200_EMIT_RB3D_BLENDCOLOR:
+ case R200_EMIT_TCL_POINT_SPRITE_CNTL:
/* These packets don't contain memory offsets */
break;
@@ -569,6 +570,7 @@
{ RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
{ RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
{ R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" },
+ { R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
};
@@ -780,11 +782,78 @@
}
}
+ /* hyper z clear */
+ if ( (flags & (RADEON_DEPTH | RADEON_STENCIL))&&(flags &
RADEON_CLEAR_HYPERZ ) ) {
+
+ int ymax=pbox[0].y2;
+ int nroftiles;
+
+ u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
+ ((clear->depth_mask & 0xff) << 24);
+
+ for ( i = 1 ; i < nbox ; i++ )
+ if (ymax<pbox[i].y2)
+ ymax=pbox[i].y2;
+
+ if ((dev_priv->flags&CHIP_IS_RV)) {
+ nroftiles = ((dev_priv->depth_pitch)/
+
(dev_priv->depth_fmt==RADEON_DEPTH_FORMAT_16BIT_INT_Z?
+ (2*16):(4*16)))*((ymax+0xf)>>4);
+ }
+ else {
+ nroftiles = ((dev_priv->depth_pitch)/
+
(dev_priv->depth_fmt==RADEON_DEPTH_FORMAT_16BIT_INT_Z?
+ (16):(2*16)))*((ymax+0xf)>>4);
+ }
+
+ /* Make sure we restore the 3D state next time.
+ * we haven't touched any "normal" state - still need this?
+ */
+ dev_priv->sarea_priv->ctx_owner = 0;
+
+ BEGIN_RING( 12 );
+ RADEON_WAIT_UNTIL_2D_IDLE();
+ OUT_RING_REG( RADEON_RB3D_DEPTHCLEARVALUE,
+ tempRB3D_DEPTHCLEARVALUE);
+ OUT_RING_REG( RADEON_RB3D_ZMASKOFFSET,
+ 0x00000000);
+
+ /* need ctlstat, otherwise get some strange black flickering */
+ OUT_RING_REG( RADEON_RB3D_ZCACHE_CTLSTAT,
RADEON_RB3D_ZC_FLUSH_ALL );
+
+ OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) );
+ /* first tile */
+ OUT_RING( 0x0 );
+ /* the number of tiles to clear */
+ OUT_RING( nroftiles );
+ if (dev_priv->flags&CHIP_IS_RV)
+ {
+ /* clear mask : chooses the clearing pattern */
+ OUT_RING( 0 );
+ } else {
+ /* FIXME : reverse engineer that for Rx00 cards */
+ OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f);
+ }
+
+ ADVANCE_RING();
+
+ if
((!(dev_priv->flags&CHIP_IS_RV))&&(dev_priv->microcode_version==UCODE_R200))
+ /* r100 and cards without hierarchical z-buffer have no
high-level z-buffer */
+ {
+ BEGIN_RING( 4 );
+ OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) );
+ OUT_RING( 0x0 ); /* First tile */
+ OUT_RING( 0x3cc0 );
+ OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f);
+ ADVANCE_RING();
+ }
+ }
+
/* We have to clear the depth and/or stencil buffers by
* rendering a quad into just those buffers. Thus, we have to
* make sure the 3D engine is configured correctly.
*/
- if ( (dev_priv->microcode_version==UCODE_R200) &&
+ else if ( (dev_priv->microcode_version==UCODE_R200) &&
(flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
int tempPP_CNTL;
Index: shared-core/drm_pciids.txt
===================================================================
RCS file: /cvs/dri/drm/shared-core/drm_pciids.txt,v
retrieving revision 1.11
diff -u -r1.11 drm_pciids.txt
--- shared-core/drm_pciids.txt 7 Nov 2004 02:19:58 -0000 1.11
+++ shared-core/drm_pciids.txt 9 Nov 2004 22:43:04 -0000
@@ -1,35 +1,35 @@
[radeon]
-0x1002 0x4136 CHIP_RS100|CHIP_IS_IGP "ATI Radeon RS100 IGP 320M"
-0x1002 0x4137 CHIP_RS200|CHIP_IS_IGP "ATI Radeon RS200 IGP"
+0x1002 0x4136 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS100 IGP 320M"
+0x1002 0x4137 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS200 IGP"
0x1002 0x4144 CHIP_R300 "ATI Radeon AD 9500 Pro"
0x1002 0x4145 CHIP_R300 "ATI Radeon AE 9700 Pro"
0x1002 0x4146 CHIP_R300 "ATI Radeon AF 9700 Pro"
0x1002 0x4147 CHIP_R300 "ATI FireGL AG Z1/X1"
-0x1002 0x4150 CHIP_RV350 "ATI Radeon AP 9600"
-0x1002 0x4151 CHIP_RV350 "ATI Radeon AQ 9600"
-0x1002 0x4152 CHIP_RV350 "ATI Radeon AR 9600"
-0x1002 0x4153 CHIP_RV350 "ATI Radeon AS 9600 AS"
-0x1002 0x4154 CHIP_RV350 "ATI FireGL AT T2"
-0x1002 0x4156 CHIP_RV350 "ATI FireGL AV T2"
-0x1002 0x4237 CHIP_RS250|CHIP_IS_IGP "ATI Radeon RS250 IGP"
+0x1002 0x4150 CHIP_RV350|CHIP_IS_RV "ATI Radeon AP 9600"
+0x1002 0x4151 CHIP_RV350|CHIP_IS_RV "ATI Radeon AQ 9600"
+0x1002 0x4152 CHIP_RV350|CHIP_IS_RV "ATI Radeon AR 9600"
+0x1002 0x4153 CHIP_RV350|CHIP_IS_RV "ATI Radeon AS 9600 AS"
+0x1002 0x4154 CHIP_RV350|CHIP_IS_RV "ATI FireGL AT T2"
+0x1002 0x4156 CHIP_RV350|CHIP_IS_RV "ATI FireGL AV T2"
+0x1002 0x4237 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS250 IGP"
0x1002 0x4242 CHIP_R200 "ATI Radeon BB R200 AIW 8500DV"
0x1002 0x4242 CHIP_R200 "ATI Radeon BC R200"
-0x1002 0x4336 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS100
Mobility U1"
-0x1002 0x4337 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS200
Mobility IGP 340M"
-0x1002 0x4437 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS250
Mobility IGP"
-0x1002 0x4964 CHIP_R250 "ATI Radeon Id R250 9000"
-0x1002 0x4965 CHIP_R250 "ATI Radeon Ie R250 9000"
-0x1002 0x4966 CHIP_R250 "ATI Radeon If R250 9000"
-0x1002 0x4967 CHIP_R250 "ATI Radeon Ig R250 9000"
+0x1002 0x4336 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon
RS100 Mobility U1"
+0x1002 0x4337 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon
RS200 Mobility IGP 340M"
+0x1002 0x4437 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon
RS250 Mobility IGP"
+0x1002 0x4964 CHIP_R250|CHIP_IS_RV "ATI Radeon Id R250 9000"
+0x1002 0x4965 CHIP_R250|CHIP_IS_RV "ATI Radeon Ie R250 9000"
+0x1002 0x4966 CHIP_R250|CHIP_IS_RV "ATI Radeon If R250 9000"
+0x1002 0x4967 CHIP_R250|CHIP_IS_RV "ATI Radeon Ig R250 9000"
0x1002 0x4C57 CHIP_RV200|CHIP_IS_MOBILITY "ATI Radeon LW RV200 Mobility 7500
M7"
0x1002 0x4C58 CHIP_RV200|CHIP_IS_MOBILITY "ATI Radeon LX RV200 Mobility FireGL
7800 M7"
-0x1002 0x4C59 CHIP_RV100|CHIP_IS_MOBILITY "ATI Radeon LY RV100 Mobility M6"
-0x1002 0x4C5A CHIP_RV100|CHIP_IS_MOBILITY "ATI Radeon LZ RV100 Mobility M6"
-0x1002 0x4C64 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Ld R250 Mobility 9000 M9"
-0x1002 0x4C65 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Le R250 Mobility 9000 M9"
-0x1002 0x4C66 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Lf R250 Mobility 9000 M9"
-0x1002 0x4C67 CHIP_R250|CHIP_IS_MOBILITY "ATI Radeon Lg R250 Mobility 9000 M9"
-0x1002 0x4E50 CHIP_RV350|CHIP_IS_MOBILITY "ATI Radeon RV300 Mobility 9600 M10"
+0x1002 0x4C59 CHIP_RV100|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon LY RV100
Mobility M6"
+0x1002 0x4C5A CHIP_RV100|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon LZ RV100
Mobility M6"
+0x1002 0x4C64 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Ld R250
Mobility 9000 M9"
+0x1002 0x4C65 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Le R250
Mobility 9000 M9"
+0x1002 0x4C66 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Lf R250
Mobility 9000 M9"
+0x1002 0x4C67 CHIP_R250|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon Lg R250
Mobility 9000 M9"
+0x1002 0x4E50 CHIP_RV350|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RV350
Mobility 9600 M10"
0x1002 0x5144 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QD R100"
0x1002 0x5145 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QE R100"
0x1002 0x5146 CHIP_R100|CHIP_SINGLE_CRTC "ATI Radeon QF R100"
@@ -44,30 +44,30 @@
0x1002 0x514F CHIP_R200 "ATI Radeon QO R200 8500 LE"
0x1002 0x5157 CHIP_RV200 "ATI Radeon QW RV200 7500"
0x1002 0x5158 CHIP_RV200 "ATI Radeon QX RV200 7500"
-0x1002 0x5159 CHIP_RV100 "ATI Radeon QY RV100 7000/VE"
-0x1002 0x515A CHIP_RV100 "ATI Radeon QZ RV100 7000/VE"
+0x1002 0x5159 CHIP_RV100|CHIP_IS_RV "ATI Radeon QY RV100 7000/VE"
+0x1002 0x515A CHIP_RV100|CHIP_IS_RV "ATI Radeon QZ RV100 7000/VE"
0x1002 0x5168 CHIP_R200 "ATI Radeon Qh R200"
0x1002 0x5169 CHIP_R200 "ATI Radeon Qi R200"
0x1002 0x516A CHIP_R200 "ATI Radeon Qj R200"
0x1002 0x516B CHIP_R200 "ATI Radeon Qk R200"
0x1002 0x516C CHIP_R200 "ATI Radeon Ql R200"
-0x1002 0x5834 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
-0x1002 0x5835 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS300
Mobility IGP"
-0x1002 0x5836 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
-0x1002 0x5837 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
-0x1002 0x5960 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5961 CHIP_RV280 "ATI Radeon RV280 9200 SE"
-0x1002 0x5962 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5963 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5964 CHIP_RV280 "ATI Radeon RV280 9200 SE"
-0x1002 0x5968 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5969 CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x596A CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x596B CHIP_RV280 "ATI Radeon RV280 9200"
-0x1002 0x5c61 CHIP_RV280|CHIP_IS_MOBILITY "ATI Radeon RV280 Mobility"
-0x1002 0x5c62 CHIP_RV280 "ATI Radeon RV280"
-0x1002 0x5c63 CHIP_RV280|CHIP_IS_MOBILITY "ATI Radeon RV280 Mobility"
-0x1002 0x5c64 CHIP_RV280 "ATI Radeon RV280"
+0x1002 0x5834 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS300 IGP"
+0x1002 0x5835 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon
RS300 Mobility IGP"
+0x1002 0x5836 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS300 IGP"
+0x1002 0x5837 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_RV "ATI Radeon RS300 IGP"
+0x1002 0x5960 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5961 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200 SE"
+0x1002 0x5962 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5963 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5964 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200 SE"
+0x1002 0x5968 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5969 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x596A CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x596B CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280 9200"
+0x1002 0x5c61 CHIP_RV280|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RV280
Mobility"
+0x1002 0x5c62 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280"
+0x1002 0x5c63 CHIP_RV280|CHIP_IS_MOBILITY|CHIP_IS_RV "ATI Radeon RV280
Mobility"
+0x1002 0x5c64 CHIP_RV280|CHIP_IS_RV "ATI Radeon RV280"
[r128]
0x1002 0x4c45 0 "ATI Rage 128 Mobility LE (PCI)"
Index: shared-core/radeon_drm.h
===================================================================
RCS file: /cvs/dri/drm/shared-core/radeon_drm.h,v
retrieving revision 1.25
diff -u -r1.25 radeon_drm.h
--- shared-core/radeon_drm.h 10 Oct 2004 05:52:19 -0000 1.25
+++ shared-core/radeon_drm.h 9 Nov 2004 22:43:05 -0000
@@ -144,7 +144,8 @@
#define RADEON_EMIT_PP_TEX_SIZE_1 74
#define RADEON_EMIT_PP_TEX_SIZE_2 75
#define R200_EMIT_RB3D_BLENDCOLOR 76
-#define RADEON_MAX_STATE_PACKETS 77
+#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
+#define RADEON_MAX_STATE_PACKETS 78
/* Commands understood by cmd_buffer ioctl. More can be added but
* obviously these can't be removed or changed:
@@ -189,6 +190,7 @@
#define RADEON_BACK 0x2
#define RADEON_DEPTH 0x4
#define RADEON_STENCIL 0x8
+#define RADEON_CLEAR_HYPERZ 0x8000000
/* Primitive types
*/
Index: shared-core/radeon_drv.h
===================================================================
RCS file: /cvs/dri/drm/shared-core/radeon_drv.h,v
retrieving revision 1.38
diff -u -r1.38 radeon_drv.h
--- shared-core/radeon_drv.h 6 Nov 2004 16:55:41 -0000 1.38
+++ shared-core/radeon_drv.h 9 Nov 2004 22:43:06 -0000
@@ -78,10 +78,12 @@
* and GL_EXT_blend_[func|equation]_separate on r200
* 1.12- Add R300 CP microcode support - this just loads the CP on r300
* (No 3D support yet - just microcode loading).
+ * 1.13- Add packed R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
+ * - Added RADEON_CLEAR_HYPERZ flag to clear ioctl.
*/
#define DRIVER_MAJOR 1
-#define DRIVER_MINOR 12
+#define DRIVER_MINOR 13
#define DRIVER_PATCHLEVEL 0
enum radeon_family {
@@ -117,6 +119,7 @@
CHIP_IS_IGP = 0x00020000UL,
CHIP_SINGLE_CRTC = 0x00040000UL,
CHIP_IS_AGP = 0x00080000UL,
+ CHIP_IS_RV = 0x00100000UL,
};
#define GET_RING_HEAD(dev_priv) DRM_READ32(
(dev_priv)->ring_rptr, 0 )
@@ -466,6 +469,7 @@
# define RADEON_STENCIL_ENABLE (1 << 7)
# define RADEON_Z_ENABLE (1 << 8)
#define RADEON_RB3D_DEPTHOFFSET 0x1c24
+#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
#define RADEON_RB3D_DEPTHPITCH 0x1c28
#define RADEON_RB3D_PLANEMASK 0x1d84
#define RADEON_RB3D_STENCILREFMASK 0x1d7c
@@ -478,11 +482,15 @@
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_Z_TEST_MASK (7 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
+# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
+# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
+# define RADEON_FORCE_Z_DIRTY (1 << 29)
# define RADEON_Z_WRITE_ENABLE (1 << 30)
+# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
@@ -590,7 +598,7 @@
# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
-#define RADEON_RB3D_ZMASKOFFSET 0x1c34
+#define RADEON_RB3D_ZMASKOFFSET 0x3234
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
@@ -644,6 +652,8 @@
# define RADEON_3D_DRAW_IMMD 0x00002900
# define RADEON_3D_DRAW_INDX 0x00002A00
# define RADEON_3D_LOAD_VBPNTR 0x00002F00
+# define RADEON_3D_CLEAR_ZMASK 0x00003200
+# define RADEON_3D_CLEAR_HIZ 0x00003700
# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
# define RADEON_CNTL_PAINT_MULTI 0x00009A00
# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
@@ -801,6 +811,8 @@
#define R200_RB3D_BLENDCOLOR 0x3218
+#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
+
/* Constants */
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
Index: shared-core/radeon_state.c
===================================================================
RCS file: /cvs/dri/drm/shared-core/radeon_state.c,v
retrieving revision 1.40
diff -u -r1.40 radeon_state.c
--- shared-core/radeon_state.c 6 Nov 2004 01:41:47 -0000 1.40
+++ shared-core/radeon_state.c 9 Nov 2004 22:43:08 -0000
@@ -271,6 +271,7 @@
case RADEON_EMIT_PP_TEX_SIZE_1:
case RADEON_EMIT_PP_TEX_SIZE_2:
case R200_EMIT_RB3D_BLENDCOLOR:
+ case R200_EMIT_TCL_POINT_SPRITE_CNTL:
/* These packets don't contain memory offsets */
break;
@@ -646,7 +647,9 @@
RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, {
RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, {
RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, {
-R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},};
+ R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, {
+ R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
+};
/* ================================================================
* Performance monitoring functions
@@ -858,11 +861,79 @@
}
}
+ /* hyper z clear */
+ if ( (flags & (RADEON_DEPTH | RADEON_STENCIL))&&(flags &
RADEON_CLEAR_HYPERZ ) ) {
+
+ int ymax=pbox[0].y2;
+ int nroftiles;
+
+ u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
+ ((clear->depth_mask & 0xff) << 24);
+
+ for ( i = 1 ; i < nbox ; i++ )
+ if (ymax<pbox[i].y2)
+ ymax=pbox[i].y2;
+
+ if ((dev_priv->flags&CHIP_IS_RV)) {
+ nroftiles = ((dev_priv->depth_pitch)/
+
(dev_priv->depth_fmt==RADEON_DEPTH_FORMAT_16BIT_INT_Z?
+ (2*16):(4*16)))*((ymax+0xf)>>4);
+ }
+ else {
+ nroftiles = ((dev_priv->depth_pitch)/
+
(dev_priv->depth_fmt==RADEON_DEPTH_FORMAT_16BIT_INT_Z?
+ (16):(2*16)))*((ymax+0xf)>>4);
+ }
+
+ /* Make sure we restore the 3D state next time.
+ * we haven't touched any "normal" state - still need this?
+ */
+ dev_priv->sarea_priv->ctx_owner = 0;
+
+ BEGIN_RING( 12 );
+ RADEON_WAIT_UNTIL_2D_IDLE();
+ OUT_RING_REG( RADEON_RB3D_DEPTHCLEARVALUE,
+ tempRB3D_DEPTHCLEARVALUE);
+ OUT_RING_REG( RADEON_RB3D_ZMASKOFFSET,
+ 0x00000000);
+
+ /* need ctlstat, otherwise get some strange black flickering */
+ OUT_RING_REG( RADEON_RB3D_ZCACHE_CTLSTAT,
RADEON_RB3D_ZC_FLUSH_ALL );
+
+ OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) );
+ /* first tile */
+ OUT_RING( 0x0 );
+ /* the number of tiles to clear */
+ OUT_RING( nroftiles );
+ if (dev_priv->flags&CHIP_IS_RV)
+ {
+ /* clear mask : chooses the clearing pattern */
+ OUT_RING( 0 );
+ } else {
+ /* FIXME : reverse engineer that for Rx00 cards */
+ OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f);
+ }
+
+ ADVANCE_RING();
+
+ if
((!(dev_priv->flags&CHIP_IS_RV))&&(dev_priv->microcode_version==UCODE_R200))
+ /* r100 and cards without hierarchical z-buffer have no
high-level z-buffer */
+ {
+ BEGIN_RING( 4 );
+ OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) );
+ OUT_RING( 0x0 ); /* First tile */
+ OUT_RING( 0x3cc0 );
+ OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f);
+ ADVANCE_RING();
+ }
+ }
+
/* We have to clear the depth and/or stencil buffers by
* rendering a quad into just those buffers. Thus, we have to
* make sure the 3D engine is configured correctly.
*/
- if ((dev_priv->microcode_version == UCODE_R200) && (flags &
(RADEON_DEPTH | RADEON_STENCIL))) {
+ else if ((dev_priv->microcode_version == UCODE_R200) &&
+ (flags & (RADEON_DEPTH | RADEON_STENCIL))) {
int tempPP_CNTL;
int tempRE_CNTL;
Index: src/mesa/drivers/dri/common/xmlpool.h
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/common/xmlpool.h,v
retrieving revision 1.8
diff -u -r1.8 xmlpool.h
--- src/mesa/drivers/dri/common/xmlpool.h 7 Oct 2004 23:30:29 -0000
1.8
+++ src/mesa/drivers/dri/common/xmlpool.h 10 Nov 2004 02:06:40 -0000
@@ -273,6 +273,14 @@
DRI_CONF_DESC_END \
DRI_CONF_OPT_END
+#define DRI_CONF_HYPERZ_DISABLED 0
+#define DRI_CONF_HYPERZ_ENABLED 1
+#define DRI_CONF_HYPERZ(def) \
+DRI_CONF_OPT_BEGIN(hyperz,bool,def) \
+ DRI_CONF_DESC(en,"Use hyperz") \
+ DRI_CONF_DESC(de,"Hyperz benutzen") \
+DRI_CONF_OPT_END
+
#define DRI_CONF_MAX_TEXTURE_UNITS(def,min,max) \
DRI_CONF_OPT_BEGIN_V(texture_units,int,def, # min ":" # max ) \
DRI_CONF_DESC(en,"Number of texture units") \
Index: src/mesa/drivers/dri/r200/r200_context.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/r200/r200_context.c,v
retrieving revision 1.34
diff -u -r1.34 r200_context.c
--- src/mesa/drivers/dri/r200/r200_context.c 3 Nov 2004 17:29:39 -0000
1.34
+++ src/mesa/drivers/dri/r200/r200_context.c 10 Nov 2004 02:06:41 -0000
@@ -266,6 +267,14 @@
rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache,
"def_max_anisotropy");
+ if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) {
+ if ( sPriv->drmMinor < 13 )
+ fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
+ "disabling.\n",sPriv->drmMinor );
+ else
+ rmesa->using_hyperz = GL_TRUE;
+ }
+
/* Init default driver functions then plug in our R200-specific functions
* (the texture functions are especially important)
*/
Index: src/mesa/drivers/dri/r200/r200_context.h
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/r200/r200_context.h,v
retrieving revision 1.24
diff -u -r1.24 r200_context.h
--- src/mesa/drivers/dri/r200/r200_context.h 3 Nov 2004 17:29:39 -0000
1.24
+++ src/mesa/drivers/dri/r200/r200_context.h 10 Nov 2004 02:06:42 -0000
@@ -102,6 +102,7 @@
struct r200_depthbuffer_state {
+ GLuint clear;
GLfloat scale;
};
@@ -930,6 +954,8 @@
/* Configuration cache
*/
driOptionCache optionCache;
+
+ GLboolean using_hyperz;
};
#define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx))
Index: src/mesa/drivers/dri/r200/r200_ioctl.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/r200/r200_ioctl.c,v
retrieving revision 1.22
diff -u -r1.22 r200_ioctl.c
--- src/mesa/drivers/dri/r200/r200_ioctl.c 2 Oct 2004 05:22:19 -0000
1.22
+++ src/mesa/drivers/dri/r200/r200_ioctl.c 10 Nov 2004 02:06:43 -0000
@@ -610,7 +610,10 @@
}
if ( mask & DD_DEPTH_BIT ) {
- if ( ctx->Depth.Mask ) flags |= RADEON_DEPTH; /* FIXME: ??? */
+ if ( ctx->Depth.Mask ) {
+ flags |= RADEON_DEPTH; /* FIXME: ??? */
+ if (rmesa->using_hyperz) flags |= RADEON_CLEAR_HYPERZ;
+ }
mask &= ~DD_DEPTH_BIT;
}
@@ -707,7 +710,7 @@
clear.flags = flags;
clear.clear_color = rmesa->state.color.clear;
- clear.clear_depth = 0; /* not used */
+ clear.clear_depth = rmesa->state.depth.clear; /* needed for hyperz */
clear.color_mask = rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK];
clear.depth_mask = rmesa->state.stencil.clear;
clear.depth_boxes = depth_boxes;
Index: src/mesa/drivers/dri/r200/r200_screen.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/r200/r200_screen.c,v
retrieving revision 1.30
diff -u -r1.30 r200_screen.c
--- src/mesa/drivers/dri/r200/r200_screen.c 10 Nov 2004 01:49:01 -0000
1.30
+++ src/mesa/drivers/dri/r200/r200_screen.c 10 Nov 2004 02:06:46 -0000
@@ -63,6 +63,7 @@
DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
DRI_CONF_MAX_TEXTURE_UNITS(4,2,6)
+ DRI_CONF_HYPERZ(true)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
@@ -81,7 +82,7 @@
DRI_CONF_NV_VERTEX_PROGRAM(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
-static const GLuint __driNConfigOptions = 14;
+static const GLuint __driNConfigOptions = 15;
#if 1
/* Including xf86PciInfo.h introduces a bunch of errors...
Index: src/mesa/drivers/dri/r200/r200_state.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/r200/r200_state.c,v
retrieving revision 1.25
diff -u -r1.25 r200_state.c
--- src/mesa/drivers/dri/r200/r200_state.c 3 Nov 2004 17:29:39 -0000
1.25
+++ src/mesa/drivers/dri/r200/r200_state.c 10 Nov 2004 02:06:48 -0000
@@ -374,6 +374,21 @@
}
}
+static void r200ClearDepth( GLcontext *ctx, GLclampd d )
+{
+ r200ContextPtr rmesa = R200_CONTEXT(ctx);
+ GLuint format = (rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &
+ R200_DEPTH_FORMAT_MASK);
+
+ switch ( format ) {
+ case R200_DEPTH_FORMAT_16BIT_INT_Z:
+ rmesa->state.depth.clear = d * 0x0000ffff;
+ break;
+ case R200_DEPTH_FORMAT_24BIT_INT_Z:
+ rmesa->state.depth.clear = d * 0x00ffffff;
+ break;
+ }
+}
static void r200DepthMask( GLcontext *ctx, GLboolean flag )
{
@@ -2315,7 +2402,7 @@
functions->BlendEquationSeparate = r200BlendEquationSeparate;
functions->BlendFuncSeparate = r200BlendFuncSeparate;
functions->ClearColor = r200ClearColor;
- functions->ClearDepth = NULL;
+ functions->ClearDepth = r200ClearDepth;
functions->ClearIndex = NULL;
functions->ClearStencil = r200ClearStencil;
functions->ClipPlane = r200ClipPlane;
Index: src/mesa/drivers/dri/r200/r200_state_init.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/r200/r200_state_init.c,v
retrieving revision 1.17
diff -u -r1.17 r200_state_init.c
--- src/mesa/drivers/dri/r200/r200_state_init.c 16 Oct 2004 03:36:14 -0000
1.17
+++ src/mesa/drivers/dri/r200/r200_state_init.c 10 Nov 2004 02:06:48 -0000
@@ -51,6 +51,7 @@
#include "r200_tex.h"
#include "r200_swtcl.h"
#include "r200_vtxfmt.h"
+#include "radeon_reg.h"
#include "xmlpool.h"
@@ -169,14 +170,16 @@
switch ( ctx->Visual.depthBits ) {
case 16:
+ rmesa->state.depth.clear = 0x0000ffff;
rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff;
depth_fmt = R200_DEPTH_FORMAT_16BIT_INT_Z;
rmesa->state.stencil.clear = 0x00000000;
break;
case 24:
+ rmesa->state.depth.clear = 0x00ffffff;
rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff;
depth_fmt = R200_DEPTH_FORMAT_24BIT_INT_Z;
- rmesa->state.stencil.clear = 0xff000000;
+ rmesa->state.stencil.clear = 0xffff0000;
break;
default:
fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
@@ -448,15 +461,25 @@
((rmesa->r200Screen->depthPitch &
R200_DEPTHPITCH_MASK) |
R200_DEPTH_ENDIAN_NO_SWAP);
+
+ if (rmesa->using_hyperz)
+ rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= RADEON_DEPTH_HYPERZ;
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
- R200_Z_TEST_LESS |
+ R200_Z_TEST_LESS |
R200_STENCIL_TEST_ALWAYS |
R200_STENCIL_FAIL_KEEP |
R200_STENCIL_ZPASS_KEEP |
R200_STENCIL_ZFAIL_KEEP |
R200_Z_WRITE_ENABLE);
+ if (rmesa->using_hyperz) {
+ rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
+ RADEON_Z_DECOMPRESSION_ENABLE;
+ if (rmesa->r200Screen->chipset & R200_CHIPSET_REAL_R200)
+ rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;
+ }
+
rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE
| R200_TEX_BLEND_0_ENABLE);
Index: src/mesa/drivers/dri/radeon/radeon_context.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/radeon/radeon_context.c,v
retrieving revision 1.25
diff -u -r1.25 radeon_context.c
--- src/mesa/drivers/dri/radeon/radeon_context.c 7 Oct 2004 23:30:30
-0000 1.25
+++ src/mesa/drivers/dri/radeon/radeon_context.c 10 Nov 2004 02:06:52
-0000
@@ -245,6 +249,14 @@
rmesa->initialMaxAnisotropy = driQueryOptionf(&rmesa->optionCache,
"def_max_anisotropy");
+ if ( driQueryOptionb( &rmesa->optionCache, "hyperz" ) ) {
+ if ( sPriv->drmMinor < 13 )
+ fprintf( stderr, "DRM version 1.%d too old to support HyperZ, "
+ "disabling.\n",sPriv->drmMinor );
+ else
+ rmesa->using_hyperz = GL_TRUE;
+ }
+
/* Init default driver functions then plug in our Radeon-specific functions
* (the texture functions are especially important)
*/
Index: src/mesa/drivers/dri/radeon/radeon_context.h
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/radeon/radeon_context.h,v
retrieving revision 1.17
diff -u -r1.17 radeon_context.h
--- src/mesa/drivers/dri/radeon/radeon_context.h 30 Sep 2004 00:08:05
-0000 1.17
+++ src/mesa/drivers/dri/radeon/radeon_context.h 10 Nov 2004 02:06:52
-0000
@@ -783,6 +788,8 @@
driOptionCache optionCache;
+ GLboolean using_hyperz;
+
/* Performance counters
*/
GLuint boxes; /* Draw performance boxes */
Index: src/mesa/drivers/dri/radeon/radeon_ioctl.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/radeon/radeon_ioctl.c,v
retrieving revision 1.15
diff -u -r1.15 radeon_ioctl.c
--- src/mesa/drivers/dri/radeon/radeon_ioctl.c 30 Sep 2004 00:08:05 -0000
1.15
+++ src/mesa/drivers/dri/radeon/radeon_ioctl.c 10 Nov 2004 02:06:53 -0000
@@ -1031,7 +1031,10 @@
}
if ( mask & DD_DEPTH_BIT ) {
- if ( ctx->Depth.Mask ) flags |= RADEON_DEPTH; /* FIXME: ??? */
+ if ( ctx->Depth.Mask ) {
+ flags |= RADEON_DEPTH; /* FIXME: ??? */
+ if (rmesa->using_hyperz) flags |= RADEON_CLEAR_HYPERZ;
+ }
mask &= ~DD_DEPTH_BIT;
}
Index: src/mesa/drivers/dri/radeon/radeon_screen.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/radeon/radeon_screen.c,v
retrieving revision 1.22
diff -u -r1.22 radeon_screen.c
--- src/mesa/drivers/dri/radeon/radeon_screen.c 10 Nov 2004 01:49:01 -0000
1.22
+++ src/mesa/drivers/dri/radeon/radeon_screen.c 10 Nov 2004 02:06:55 -0000
@@ -60,6 +60,7 @@
DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
+ DRI_CONF_HYPERZ(true)
DRI_CONF_SECTION_END
DRI_CONF_SECTION_QUALITY
DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
@@ -74,7 +75,7 @@
DRI_CONF_NO_RAST(false)
DRI_CONF_SECTION_END
DRI_CONF_END;
-static const GLuint __driNConfigOptions = 11;
+static const GLuint __driNConfigOptions = 12;
#if 1
/* Including xf86PciInfo.h introduces a bunch of errors...
Index: src/mesa/drivers/dri/radeon/radeon_state_init.c
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/radeon/radeon_state_init.c,v
retrieving revision 1.10
diff -u -r1.10 radeon_state_init.c
--- src/mesa/drivers/dri/radeon/radeon_state_init.c 30 Sep 2004 00:08:05
-0000 1.10
+++ src/mesa/drivers/dri/radeon/radeon_state_init.c 10 Nov 2004 02:06:57
-0000
@@ -45,6 +45,7 @@
#include "radeon_tex.h"
#include "radeon_swtcl.h"
#include "radeon_vtxfmt.h"
+#include "radeon_reg.h"
#include "xmlpool.h"
@@ -174,7 +175,7 @@
rmesa->state.depth.clear = 0x00ffffff;
rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff;
depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
- rmesa->state.stencil.clear = 0xff000000;
+ rmesa->state.stencil.clear = 0xffff0000;
break;
default:
fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
@@ -329,6 +330,9 @@
((rmesa->radeonScreen->depthPitch &
RADEON_DEPTHPITCH_MASK) |
RADEON_DEPTH_ENDIAN_NO_SWAP);
+
+ if (rmesa->using_hyperz)
+ rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= RADEON_DEPTH_HYPERZ;
rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
RADEON_Z_TEST_LESS |
@@ -338,6 +342,13 @@
RADEON_STENCIL_ZFAIL_KEEP |
RADEON_Z_WRITE_ENABLE);
+ if (rmesa->using_hyperz) {
+ rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE
|
+ RADEON_Z_DECOMPRESSION_ENABLE;
+ if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)
+ rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;
+ }
+
rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
RADEON_ANTI_ALIAS_NONE);
Index: src/mesa/drivers/dri/radeon/server/radeon_reg.h
===================================================================
RCS file: /cvs/mesa/Mesa/src/mesa/drivers/dri/radeon/server/radeon_reg.h,v
retrieving revision 1.4
diff -u -r1.4 radeon_reg.h
--- src/mesa/drivers/dri/radeon/server/radeon_reg.h 21 Oct 2003 06:05:51
-0000 1.4
+++ src/mesa/drivers/dri/radeon/server/radeon_reg.h 10 Nov 2004 02:07:01
-0000
@@ -1555,6 +1555,7 @@
# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18)
# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18)
# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18)
+# define RADEON_DEPTH_HYPERZ (3 << 16)
#define RADEON_RB3D_PLANEMASK 0x1d84
#define RADEON_RB3D_ROPCNTL 0x1d80
# define RADEON_ROP_MASK (15 << 8)
@@ -1600,6 +1601,7 @@
# define RADEON_Z_TEST_NEQUAL (6 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
# define RADEON_Z_TEST_MASK (7 << 4)
+# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
# define RADEON_STENCIL_TEST_NEVER (0 << 12)
# define RADEON_STENCIL_TEST_LESS (1 << 12)
# define RADEON_STENCIL_TEST_LEQUAL (2 << 12)
@@ -1633,6 +1635,7 @@
# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
# define RADEON_FORCE_Z_DIRTY (1 << 29)
# define RADEON_Z_WRITE_ENABLE (1 << 30)
+# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
#define RADEON_RE_LINE_PATTERN 0x1cd0
# define RADEON_LINE_PATTERN_MASK 0x0000ffff
# define RADEON_LINE_REPEAT_COUNT_SHIFT 16
Index: stencil_wrap.c
===================================================================
RCS file: /cvs/mesa/Mesa/progs/tests/stencil_wrap.c,v
retrieving revision 1.1
diff -u -r1.1 stencil_wrap.c
--- stencil_wrap.c 4 Nov 2004 22:32:41 -0000 1.1
+++ stencil_wrap.c 10 Nov 2004 02:18:16 -0000
@@ -177,6 +177,7 @@
}
glEnd();
+ glClear(GL_DEPTH_BUFFER_BIT);
glStencilFunc(GL_EQUAL, (max_stencil - 4), ~0);
glBegin(GL_QUADS);
glColor3f( 0.5, 0.5, 0.5 );
