Hi all,
I've written the initial code for PCI express for the X300 (patch
attached), it sets the registers up somewhat like the normal PCI gart
code, and like what fglrx seems to do as well...
Now my problem at the moment is I can't get fglrx to work on my X300 at
all either, it hangs... (XP works fine..), I'm going to install FC3 as
well as ubuntu just to get a second opinion :-)
I've also attached a patch to hw_script that reads the PCIE registers that
can be used with fglrx...
Dave.
--
David Airlie, Software Engineer
http://www.skynet.ie/~airlied / airlied at skynet.ie
Linux kernel - DRI, VAX / pam_smb / ILUG
Index: linux-core/drmP.h
===================================================================
RCS file: /cvsroot/r300/r300_driver/drm/linux-core/drmP.h,v
retrieving revision 1.4
diff -u -r1.4 drmP.h
--- linux-core/drmP.h 13 May 2005 18:30:46 -0000 1.4
+++ linux-core/drmP.h 31 May 2005 07:00:33 -0000
@@ -1025,6 +1025,11 @@
return pci_find_capability(dev->pdev, PCI_CAP_ID_AGP);
}
+static __inline__ int drm_device_is_pcie(drm_device_t *dev)
+{
+ return pci_find_capability(dev->pdev, PCI_CAP_ID_EXP);
+}
+
static __inline__ void drm_core_dropmap(struct drm_map *map)
{
}
Index: shared-core/drm_pciids.txt
===================================================================
RCS file: /cvsroot/r300/r300_driver/drm/shared-core/drm_pciids.txt,v
retrieving revision 1.11
diff -u -r1.11 drm_pciids.txt
--- shared-core/drm_pciids.txt 4 Mar 2005 00:14:42 -0000 1.11
+++ shared-core/drm_pciids.txt 31 May 2005 07:00:34 -0000
@@ -62,6 +62,7 @@
0x1002 0x516A CHIP_R200 "ATI Radeon Qj R200"
0x1002 0x516B CHIP_R200 "ATI Radeon Qk R200"
0x1002 0x516C CHIP_R200 "ATI Radeon Ql R200"
+0x1002 0x5460 CHIP_RV350 "ATI Radeon X300"
0x1002 0x5834 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
0x1002 0x5835 CHIP_RS300|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS300
Mobility IGP"
0x1002 0x5836 CHIP_RS300|CHIP_IS_IGP "ATI Radeon RS300 IGP"
Index: shared-core/radeon_cp.c
===================================================================
RCS file: /cvsroot/r300/r300_driver/drm/shared-core/radeon_cp.c,v
retrieving revision 1.7
diff -u -r1.7 radeon_cp.c
--- shared-core/radeon_cp.c 19 Apr 2005 21:05:18 -0000 1.7
+++ shared-core/radeon_cp.c 31 May 2005 07:00:37 -0000
@@ -823,6 +823,12 @@
return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
}
+static int RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
+{
+ RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
+ return RADEON_READ(RADEON_PCIE_DATA);
+}
+
#if RADEON_FIFO_DEBUG
static void radeon_status(drm_radeon_private_t * dev_priv)
{
@@ -1231,11 +1237,35 @@
RADEON_ISYNC_CPSCRATCH_IDLEGUI));
}
+/* Enable or disable PCI-E GART on the chip */
+static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
+{
+ u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
+ if (on) {
+ RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
RADEON_PCIE_TX_GART_EN | RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD |
RADEON_PCIE_TX_GART_CHK_RW_VALID_EN);
+
+ RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
dev_priv->bus_pci_gart);
+ RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
dev_priv->gart_vm_start);
+ RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
dev_priv->gart_vm_start
+ + dev_priv->gart_size - 1);
+
+ RADEON_WRITE(RADEON_MC_AGP_LOCATION, 0xffffffc0); /* ?? */
+ } else {
+ RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp &
~RADEON_PCIE_TX_GART_EN);
+ }
+}
+
/* Enable or disable PCI GART on the chip */
static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
{
u32 tmp = RADEON_READ(RADEON_AIC_CNTL);
+ if (dev_priv->flags & CHIP_IS_PCIE)
+ {
+ radeon_set_pciegart(dev_priv, on);
+ return;
+ }
+
if (on) {
RADEON_WRITE(RADEON_AIC_CNTL,
tmp | RADEON_PCIGART_TRANSLATE_EN);
@@ -2051,8 +2081,11 @@
if (drm_device_is_agp(dev))
dev_priv->flags |= CHIP_IS_AGP;
+ if (drm_device_is_pcie(dev))
+ dev_priv->flags |= CHIP_IS_PCIE;
+
DRM_DEBUG("%s card detected\n",
- ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : "PCI"));
+ ((dev_priv->flags & CHIP_IS_AGP) ? "AGP" : (((dev_priv->flags
& CHIP_IS_PCIE) ? "PCIE" : "PCI"))));
#if defined(__linux__)
/* Check if we need a reset */
Index: shared-core/radeon_drv.h
===================================================================
RCS file: /cvsroot/r300/r300_driver/drm/shared-core/radeon_drv.h,v
retrieving revision 1.12
diff -u -r1.12 radeon_drv.h
--- shared-core/radeon_drv.h 3 Mar 2005 04:40:21 -0000 1.12
+++ shared-core/radeon_drv.h 31 May 2005 07:00:40 -0000
@@ -126,6 +126,7 @@
CHIP_SINGLE_CRTC = 0x00040000UL,
CHIP_IS_AGP = 0x00080000UL,
CHIP_HAS_HIERZ = 0x00100000UL,
+ CHIP_IS_PCIE = 0x00200000UL,
};
#define GET_RING_HEAD(dev_priv) DRM_READ32(
(dev_priv)->ring_rptr, 0 )
@@ -364,6 +365,24 @@
#define RADEON_CRTC2_OFFSET 0x0324
#define RADEON_CRTC2_OFFSET_CNTL 0x0328
+#define RADEON_PCIE_INDEX 0x0030
+#define RADEON_PCIE_DATA 0x0034
+#define RADEON_PCIE_TX_GART_CNTL 0x10
+# define RADEON_PCIE_TX_GART_EN (1 << 0)
+# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
+# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
+# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
+# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
+# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
+# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
+#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
+#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
+#define RADEON_PCIE_TX_GART_BASE 0x13
+#define RADEON_PCIE_TX_GART_START_LO 0x14
+#define RADEON_PCIE_TX_GART_START_HI 0x15
+#define RADEON_PCIE_TX_GART_END_LO 0x16
+#define RADEON_PCIE_TX_GART_END_HI 0x17
+
#define RADEON_MPP_TB_CONFIG 0x01c0
#define RADEON_MEM_CNTL 0x0140
#define RADEON_MEM_SDRAM_MODE_REG 0x0158
@@ -874,6 +893,13 @@
RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
} while (0)
+#define RADEON_WRITE_PCIE( addr, val ) \
+do { \
+ RADEON_WRITE8( RADEON_PCIE_INDEX, \
+ ((addr) & 0xff)); \
+ RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
+} while (0)
+
extern int radeon_preinit(struct drm_device *dev, unsigned long flags);
extern int radeon_postcleanup(struct drm_device *dev);
Index: Makefile
===================================================================
RCS file: /cvsroot/volodya-project/hw_script/Makefile,v
retrieving revision 1.4
diff -u -r1.4 Makefile
--- Makefile 11 Dec 2001 02:24:41 -0000 1.4
+++ Makefile 31 May 2005 07:22:00 -0000
@@ -1,7 +1,7 @@
-PCIUTILS_LIB=../../pciutils-2.1.8/lib/
+PCIUTILS_LIB=/usr/include/pci
-INCLUDES=-I/usr/X11/include -I$(PCIUTILS_LIB)
+INCLUDES=-I/usr/X11/include -I$(PCIUTILS_LIB) -I/usr/include/tcl8.4
-I/usr/include/tk8.4
DEFINES=
@@ -11,8 +11,8 @@
LIBS=-lm -ldl -L$(PCIUTILS_LIB) -lpci
-TCLLIBS=-ltcl8.3
-TKLIBS=-ltk8.3
+TCLLIBS=-ltcl8.4
+TKLIBS=-ltk8.4
all: hw_script hw_script_tk
Index: read_radeon.scp
===================================================================
RCS file: /cvsroot/volodya-project/hw_script/read_radeon.scp,v
retrieving revision 1.4
diff -u -r1.4 read_radeon.scp
--- read_radeon.scp 27 Dec 2001 01:25:28 -0000 1.4
+++ read_radeon.scp 31 May 2005 07:22:01 -0000
@@ -4,7 +4,7 @@
# find RADEON All-in-Wonder. Replace ids with your own.
set PCI_VENDOR_ID 0x1002
-set PCI_DEVICE_ID 0x5144
+set PCI_DEVICE_ID 0x5460
scan_pci {
if { ($VENDOR_ID == $PCI_VENDOR_ID) && ($DEVICE_ID == $PCI_DEVICE_ID) }
{
@@ -39,11 +39,15 @@
set CLOCK_CNTL2 [expr (0x8+2)]
set CLOCK_CNTL_DATA [expr (0xC)]
+set PCIE_CNTL0 [expr (0x30)]
+set PCIE_CNTL_DATA [expr (0x34)]
+
global CLOCK_CNTL0
global CLOCK_CNTL1
global CLOCK_CNTL2
global CLOCK_CNTL_DATA
-
+global PCIE_CNTL0
+global PCIE_CNTL_DATA
set device_id [read_long reg_aperture $DEVICE_ID]
@@ -51,6 +55,16 @@
set vendor_id [read_long reg_aperture $VENDOR_ID]
puts "VENDOR_ID([long_to_hex $VENDOR_ID]): $vendor_id=[long_to_char
$vendor_id]"
+proc radeon_read_pcie_reg {reg} {
+global PCIE_CNTL0
+global PCIE_CNTL_DATA
+#set old_index_value0 [read_byte reg_aperture $CLOCK_CNTL0]
+#set old_index_value1 [read_byte reg_aperture $CLOCK_CNTL1]
+#puts "$old_index_value0 $old_index_value1"
+write_byte reg_aperture $PCIE_CNTL0 [expr $reg]
+return [read_long reg_aperture $PCIE_CNTL_DATA]
+}
+
proc radeon_read_pll_reg {reg} {
global CLOCK_CNTL0
global CLOCK_CNTL1
@@ -89,6 +103,16 @@
puts "$reg_name= [set "$reg_name.value"] = [long_to_binary [set
"$reg_name.value"]]"
}
+proc radeon_dump_pcie_regs {} {
+puts "Dump of PCIE indirect registers starting from 0"
+for { set i 0 } { $i < 255} { incr i } {
+ puts -nonewline " [radeon_read_pcie_reg $i]"
+ if { ($i & 0x3)==0x3 } {
+ puts ""
+ }
+ }
+}
+
proc radeon_dump_pll_regs {} {
puts "Dump of PLL registers starting from 0"
for { set i 0 } { $i < 32} { incr i } {
@@ -99,6 +123,7 @@
}
}
+radeon_dump_pcie_regs
radeon_dump_pll_regs
set PPLL_REF_DIV 0x003
