On Thu, 16 Jun 2005 14:22:36 +0200 Nicolai Haehnle <[EMAIL PROTECTED]> wrote:
> On Thursday 16 June 2005 13:41, Aapo Tahkola wrote: > > Update of /cvsroot/r300/r300_driver/r300 > > In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv6333 > > > > Modified Files: > > r300_reg.h r300_state.c > > Log Message: > > Use depth tiling. > > Will this work with software fallbacks? Im not quite sure but more recent r200_span.c has few words about it. Attached patch enables color tiling in case someone wants to play with it. -- Aapo Tahkola
--- radeon_driver.c.orig Fri Jun 10 05:24:35 2005 +++ radeon_driver.c Tue Jun 21 18:13:31 2005 @@ -4745,10 +4745,6 @@ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling disabled for 2nd head\n"); info->allowColorTiling = FALSE; } - else if ((info->allowColorTiling) && (info->ChipFamily >= CHIP_FAMILY_R300)) { - xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling disabled for r300 and newer chips\n"); - info->allowColorTiling = FALSE; - } else if ((info->allowColorTiling) && (info->FBDev)) { xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Color tiling not supported with UseFBDev option\n"); @@ -5631,6 +5627,11 @@ if (!info->IsSecondary) RADEONChangeSurfaces(pScrn); + if (info->ChipFamily >= CHIP_FAMILY_R300) { + unsigned char *RADEONMMIO = info->MMIO; + OUTREG(0x180, INREG(0x180) | 0x1100); + } + if(info->MergedFB) { /* need this here to fix up sarea values */ RADEONAdjustFrameMerged(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0); @@ -6133,7 +6134,12 @@ drmRadeonSurfaceAlloc drmsurfalloc; drmsurfalloc.size = bufferSize; drmsurfalloc.address = info->frontOffset; - drmsurfalloc.flags = swap_pattern | (width_bytes / 16) | color_pattern; + + if (IS_R300_VARIANT) + drmsurfalloc.flags = swap_pattern | (width_bytes / 8) | color_pattern; + else + drmsurfalloc.flags = swap_pattern | (width_bytes / 16) | color_pattern; + retvalue = drmCommandWrite(info->drmFD, DRM_RADEON_SURF_ALLOC, &drmsurfalloc, sizeof(drmsurfalloc)); if (retvalue < 0) @@ -6172,7 +6178,10 @@ /* we don't need anything like WaitForFifo, no? */ if (!info->IsSecondary) { if (info->tilingEnabled) { - surf_info = swap_pattern | (width_bytes / 16) | color_pattern; + if (IS_R300_VARIANT) + surf_info = swap_pattern | (width_bytes / 8) | color_pattern; + else + surf_info = swap_pattern | (width_bytes / 16) | color_pattern; } OUTREG(RADEON_SURFACE0_INFO, surf_info); OUTREG(RADEON_SURFACE0_LOWER_BOUND, 0); @@ -7088,10 +7097,16 @@ save->crtc_offset = 0; save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL); if (info->tilingEnabled) { - save->crtc_offset_cntl |= RADEON_CRTC_TILE_EN; + if (IS_R300_VARIANT) + save->crtc_offset_cntl |= 0x8e00; + else + save->crtc_offset_cntl |= RADEON_CRTC_TILE_EN; } else { - save->crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; + if (IS_R300_VARIANT) + save->crtc_offset_cntl &= ~0x8e00; + else + save->crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; } save->crtc_pitch = (((pScrn->displayWidth * pScrn->bitsPerPixel) + @@ -7273,10 +7288,16 @@ save->crtc2_offset = 0; save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL) & RADEON_CRTC_OFFSET_FLIP_CNTL; if (info->tilingEnabled) { - save->crtc2_offset_cntl |= RADEON_CRTC_TILE_EN; + if (IS_R300_VARIANT) + save->crtc2_offset_cntl |= 0x8e00; + else + save->crtc2_offset_cntl |= RADEON_CRTC_TILE_EN; } else { - save->crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN; + if (IS_R300_VARIANT) + save->crtc2_offset_cntl &= ~0x8e00; + else + save->crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN; } /* this should be right */