W dniu 26 grudnia 2009 02:46 użytkownik Rafał Miłecki <zaj...@gmail.com> napisał: > W dniu 24 grudnia 2009 08:19 użytkownik Michel Dänzer > <mic...@daenzer.net> napisał: >> I suspect the delay is more likely due to the workqueue than the >> interrupt itself. Way back when I implemented DRI1 tear-free buffer >> swaps for i945, I had to use a tasklet to reliably do work within the >> vertical blank period. > > I can not use tasklet as I need to sleep in setting engine function > (AtomBIOS command does it). > > First of all I converted Alex's code to take requested mode before > handling IRQ. Unfortunately that didn't help. Then I've converted > VBLANK sync from work queue to wait_event_interruptible_timeout and > wake_up_interruptible (btw. code seems much cleaner). This also didn't > help. > > There are some my experiments with engine. Reclocking between: > 1) 110MHz and 680MHz - 1 corrupted frame on every reclock > 2) 200MHz and 680MHz - 1 corrupted frame on almost every reclock > 3) 250MHz and 680MHz - no corruptions > 4) 340MHz and 680MHz - no corruptions > 5) 630MHz and 680MHz - no corruptions > > Maybe it's just downclocking to very low 110MHz that shouldn't happen? > My GPU works fine on this engine clock (no corruptions) but still > maybe reclocking to so low value can not be performed without > corruption? > > I don't think anymore it's timing related issue.
[ 12.638290] [drm] 6 Power State(s) [ 12.638292] [drm] State 0 Default (default) [ 12.638293] [drm] 16 PCIE Lanes [ 12.638295] [drm] 3 Clock Mode(s) [ 12.638297] [drm] 0 engine/memory: 680000/800000 [ 12.638298] [drm] 1 engine/memory: 680000/800000 [ 12.638300] [drm] 2 engine/memory: 680000/800000 [ 12.638302] [drm] State 1 Performance [ 12.638303] [drm] 16 PCIE Lanes [ 12.638304] [drm] 3 Clock Mode(s) [ 12.638306] [drm] 0 engine/memory: 110000/405000 [ 12.638308] [drm] 1 engine/memory: 300000/405000 [ 12.638310] [drm] 2 engine/memory: 680000/800000 [ 12.638311] [drm] State 2 Battery [ 12.638313] [drm] 16 PCIE Lanes [ 12.638314] [drm] 3 Clock Mode(s) [ 12.638316] [drm] 0 engine/memory: 110000/405000 [ 12.638317] [drm] 1 engine/memory: 110000/405000 [ 12.638319] [drm] 2 engine/memory: 300000/405000 [ 12.638321] [drm] State 3 Default [ 12.638322] [drm] 16 PCIE Lanes [ 12.638323] [drm] 3 Clock Mode(s) [ 12.638325] [drm] 0 engine/memory: 300000/400000 [ 12.638327] [drm] 1 engine/memory: 550000/700000 [ 12.638328] [drm] 2 engine/memory: 550000/700000 [ 12.638330] [drm] State 4 Performance [ 12.638331] [drm] 16 PCIE Lanes [ 12.638333] [drm] 3 Clock Mode(s) [ 12.638334] [drm] 0 engine/memory: 300000/800000 [ 12.638336] [drm] 1 engine/memory: 300000/800000 [ 12.638338] [drm] 2 engine/memory: 680000/800000 [ 12.638339] [drm] State 5 Battery [ 12.638341] [drm] 16 PCIE Lanes [ 12.638342] [drm] 3 Clock Mode(s) [ 12.638344] [drm] 0 engine/memory: 300000/405000 [ 12.638345] [drm] 1 engine/memory: 300000/405000 [ 12.638347] [drm] 2 engine/memory: 300000/405000 -- Rafał ------------------------------------------------------------------------------ This SF.Net email is sponsored by the Verizon Developer Community Take advantage of Verizon's best-in-class app development support A streamlined, 14 day to market process makes app distribution fast and easy Join now and get one step closer to millions of Verizon customers http://p.sf.net/sfu/verizon-dev2dev -- _______________________________________________ Dri-devel mailing list Dri-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/dri-devel
