2009/12/29 Luca Tettamanti <kronos...@gmail.com>:
> 2009/12/28 Alex Deucher <alexdeuc...@gmail.com>:
>> 2009/12/28 Luca Tettamanti <kronos...@gmail.com>:
>>> On Mon, Dec 28, 2009 at 01:32:24PM -0500, Alex Deucher wrote:
>>>> 2009/12/28 Luca Tettamanti <kronos...@gmail.com>:
>>>> > 2009/12/28 Alex Deucher <alexdeuc...@gmail.com>:
>>>> >> On Mon, Dec 28, 2009 at 5:53 AM, Luca Tettamanti <kronos...@gmail.com>
>>>> >> wrote:
>>>> >>> Unless there are more subtleties all is needed it to enabled the
>>>> >>> interrupt and catch it in r600_irq_process.
>>>> >>
>>>> >> That's pretty much it. Pre-r6xx asics have a GUI interrupt as well.
>>>> >> I can look up the details for that if they are not already documented.
>>>> >
>>>> > I can't find a way to ack the interrupt; I see
>>>> > RADEON_GUI_IDLE_INT_TEST_ACK but I think it's for pre-r6xx cards,
>>>> > right?
>>>>
>>>> You don't have to ACK it as the CP generates the interrupt in
>>>> software; similar to the sw interrupts used for fences.
>>>
>>> Ok, good: I've got the stub running on my M76. r100 and rs600 parts are
>>> untested. Comments?
>>>
>>
>> Looks pretty good. I've included the proper defines from the register
>> database below and you'll need to ack the gui idle interrupts on
>> pre-r600 chips. Now you just have to do something when you get the
>> idle interrupt.
> [...]
>>> --- linux-2.6.git.orig/drivers/gpu/drm/radeon/r100.c 2009-12-28
>>> 22:30:59.079748392 +0100
>>> +++ linux-2.6.git/drivers/gpu/drm/radeon/r100.c 2009-12-28
>>> 22:41:07.803741755 +0100
>>> @@ -246,6 +246,9 @@
>>> if (rdev->irq.sw_int) {
>>> tmp |= RADEON_SW_INT_ENABLE;
>>> }
>>> + if (rdev->irq.idle_int) {
>>> + tmp |= RADEON_GUI_IDLE_INT_ENABLE;
>>> + }
>>> if (rdev->irq.crtc_vblank_int[0]) {
>>> tmp |= RADEON_CRTC_VBLANK_MASK;
>>> }
>>> @@ -278,7 +281,8 @@
>>> uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
>>> uint32_t irq_mask = RADEON_SW_INT_TEST |
>>> RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
>>> - RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
>>> + RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT |
>>> + RADEON_GUI_IDLE_INT_TEST_ACK;
>>>
>>> if (irqs) {
>>> WREG32(RADEON_GEN_INT_STATUS, irqs);
>>> @@ -318,6 +322,9 @@
>>> queue_hotplug = true;
>>> DRM_DEBUG("HPD2\n");
>>> }
>>> + if (status & RADEON_GUI_IDLE_INT_TEST_ACK) {
>>> + DRM_DEBUG("GUI idle\n");
>>> + }
>>
>>
>> You'll need to ack this on pre-r6xx.
>
> Clear on write? I've included the relevant bit in irq_mask, so r100
> should be ok.
Right. missed that. should be ok.
>
>>> --- linux-2.6.git.orig/drivers/gpu/drm/radeon/rs600.c 2009-12-28
>>> 22:32:30.927884090 +0100
>>> +++ linux-2.6.git/drivers/gpu/drm/radeon/rs600.c 2009-12-28
>>> 22:46:23.211897501 +0100
>>> @@ -318,6 +318,9 @@
>>> if (rdev->irq.sw_int) {
>>> tmp |= S_000040_SW_INT_EN(1);
>>> }
>>> + if (rdev->irq.idle_int) {
>>> + tmp |= S_000040_GUI_IDLE(1);
>>> + }
>>> if (rdev->irq.crtc_vblank_int[0]) {
>>> mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
>>> }
>>> @@ -411,6 +414,9 @@
>>> queue_hotplug = true;
>>> DRM_DEBUG("HPD2\n");
>>> }
>>> + if (G_000044_GUI_IDLE_STAT(status)) {
>>> + DRM_DEBUG("GUI idle\n");
>>> + }
>>
>> You'll need to ACK this on pre-r6xx chips.
>
> Ok, I was mislead by the name of the file ;-)
> rs600 = sort-of-r500?
yes. rs600 (and rs690/rs740) have avivo display engines, but r4xx 3d
engines. The irq stuff is the same as r5xx.
Alex
------------------------------------------------------------------------------
This SF.Net email is sponsored by the Verizon Developer Community
Take advantage of Verizon's best-in-class app development support
A streamlined, 14 day to market process makes app distribution fast and easy
Join now and get one step closer to millions of Verizon customers
http://p.sf.net/sfu/verizon-dev2dev
--
_______________________________________________
Dri-devel mailing list
Dri-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/dri-devel
