On 8 May 2016 at 13:19, Chang, Abner (HPS SW/FW Technologist) <[email protected]> wrote: > Hi Jordan, > The UEFI/PI ECR for RISC-V is ready but not yet send to UEFI for review. I > have been told to upstream RISC-V code first and then submit the spec. I will > confirm this again.
Hello Abner, Is the PE/COFF support that you implemented based on the PE/COFF spec? Regards, Ard. _______________________________________________ edk2-devel mailing list [email protected] https://lists.01.org/mailman/listinfo/edk2-devel
