Hi, experts:
I am studying Intel 64 and IA-32 Architectures Software Developer's
Manual Volume 3A.pdf .
I have a few questions about Multi-processor management.
1. 7.5 Multi-processor initialization In Chapter 7
......
The mechanism for carrying out the MP initialization protocol differs
depending on the IA-32 processor family, as follows:
(1) For P6 family processors- The selection of the BSP and APs (see
Section
7.5.1, "BSP and AP Processors") is handled through arbitration on the
APIC bus,
using BIPI and FIPI messages. See Appendix C, "MP Initialization For P6
Family
Processors,"for a complete discussion of MP initialization for P6 family
processors.
(2) Intel Xeon processors with family, model, and stepping IDs up to
F09H-
The selection of the BSP and APs (see Section 7.5.1, "BSP and AP
Processors") is
handled through arbitration on the systembus, using BIPI and FIPI
messages
(see Section 7.5.3, "MP Initialization Protocol Algorithm for Intel Xeon
Processors").
(3) Intel Xeon processors with family, model, and stepping IDs of F0AH
and
beyond, 6E0H and beyond, 6F0H and beyond - The selection of the BSP and
APs is handled through a special system bus cycle, without using BIPI
and FIPI
message arbitration (see Section 7.5.3, "MP Initialization Protocol
Algorithm for Intel Xeon Processors").
So, current CPU(such as: bay trail ) uses method (2) or method (3) ?
2. When to halt non-BSP cores in UEFI Code?
Usually only BSP runs BIOS code.
So when and where to halt non-BSP cores in UEFI Code?
In CPU PEIM? Or SEC phase code?
Best wishes,
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