I am quoting a section from the Electric user manual in Ch 7, section 7-4-2. The line in bold concerns me:
Scalable Transistors The MOSIS CMOS technology has two transistor nodes that can take a text attribute to control their width. These transistors also have contacts built into them. Without the text attribute, the maximum width is displayed. However, by adding a "width" attribute, they shrink to that size. Note that the ports never change location, thus allowing them to scale without triggering constraints. The scaling feature of these transistors is not very useful because *it is not possible to parameterize layout cells*. What does it mean that it is not possible to parametrize layout cells? From my experience, p-cells or paremetrized cells are cells where you can control some "parameter" of the device, such as length, width and such. And I see that Electric does have this capability, as I have placed MOS etc cells and indeed changed their length and width. So could someone please explain what this statement in the manual means? Does it, maybe mean that a user cannot create a custom parametrized cells library? I hope this is not true. Thanks Yusuf -- You received this message because you are subscribed to the Google Groups "Electric VLSI Editor" group. To view this discussion on the web visit https://groups.google.com/d/msg/electricvlsi/-/QkeGBLp89jkJ. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/electricvlsi?hl=en.
