At 09:03 PM 6/16/2012, you wrote:
I am quoting a section from the Electric user manual in Ch 7,
section 7-4-2. The line in bold concerns me:
Scalable Transistors
The MOSIS CMOS technology has two transistor nodes that can take a
text attribute to control their width. These transistors also have
contacts built into them. Without the text attribute, the maximum
width is displayed. However, by adding a "width" attribute, they
shrink to that size. Note that the ports never change location, thus
allowing them to scale without triggering constraints. The scaling
feature of these transistors is not very useful because it is not
possible to parameterize layout cells.
What does it mean that it is not possible to parametrize layout
cells? From my experience, p-cells or paremetrized cells are cells
where you can control some "parameter" of the device, such as
length, width and such. And I see that Electric does have this
capability, as I have placed MOS etc cells and indeed changed their
length and width.
So could someone please explain what this statement in the manual
means? Does it, maybe mean that a user cannot create a custom
parametrized cells library? I hope this is not true.
Although Cadence does have "pcells" that can change their internal
geometry according to parameters on the pcell, Electric does not have
this capability. You cannot put a parameter onto an arbitrary
Electric Cell, and then expect the geometry in that cell to alter
according to the parameter value.
There are limited exceptions to this rule. For example, it *IS*
possible to create parameters, especially in the schematics side of
things, which will propagate down the hierarchy and be used
somewhere, for example in a Spice deck. But the actual geometry, as
seen on the display, cannot be affected in this way.
So the manual is telling you that the "scalable transistors" are an
exception to the "no geometry can be parameterizable" rule, but a
minor one, and one that doesn't give you the full power that you
might want. For example, the "scalable transistors" have to be made
as wide as the widest expected parameter value, because they can only
really shrink from their placed size, not grow. And since other
parts of the layout cannot be parameterized, the scalable transistors
actually find little use in common practice.
-Steve
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