A recent thread on emc-users discussed the value of hal drivers having 
dedicated functions to read & write the gpios, without reading & writing 
everything else (ie: encoders, stepgens, pwmgens).  The utility of this 
interface is clear.  This interface is easy to provide for hardware 
where the I/O is threadsafe, such as PCI cards, but it's harder to do it 
on hardware where the I/O is not threadsafe, such as EPP.  To ensure 
atomicity in RTAI of the EPP address cycles and the subsequent EPP data 
cycles, the driver must turn off interrupts.


I've implemented this and it works well.  The code is in my experimental 
  hostmot2 branch here:

<https://code.launchpad.net/~seb-highlab/emc/hostmot2>

The interesting bits are in hm2_llio_read() and hm2_llio_write(), 
starting on line 649 of hostmot2.c:

<http://bazaar.launchpad.net/~seb-highlab/emc/hostmot2/annotate/473?file_id=hostmot2.comp-20080324150436-3zy8ulsbxdch5jua-5>

The code turns off interrupts before starting an EPP transaction and 
re-enables interrupts when the transaction is finished.  (It only does 
this for the EPP boards, the PCI boards dont need it.)


A typical EPP transaction for this driver consists of two address cycles 
and 16 data cycles, for a total of about 20 or 25 microseconds of no 
interrupts.  It occasionally (rarely) spikes as high as 75 microseconds.


There's a judgement call here, and I seek your advice.  Is 25 
microseconds too long to run with interrupts off?


-- 
Sebastian Kuzminsky
Cryogenic travel has improved since then...  I woke screaming in a
translucent box.  “There, there,” said the box. “Everything will be all
right. Have some coffee.”  -- Ken Macleod, "Who's afraid of Wolf 359"
<http://outofthiseos.typepad.com/blog/files/KenMacleodWhosAfraidofWolf359.htm>

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