Jeff Epler wrote: > On Wed, Aug 13, 2008 at 01:58:50AM -0600, Sebastian Kuzminsky wrote: > >>A typical EPP transaction for this driver consists of two address cycles >>and 16 data cycles, for a total of about 20 or 25 microseconds of no >>interrupts. It occasionally (rarely) spikes as high as 75 microseconds. >> >> >>There's a judgement call here, and I seek your advice. Is 25 >>microseconds too long to run with interrupts off? > > > It doesn't seem like this would mix well with software step generation > in the fast thread. Items like that--where the fpga doesn't support > the specific kind of I/O, but the PC is fast enough to do it in the > base_thread--is the whole reason to run GPIO in the fast thread. But, if you have a 7i43, it is not likely you'd be doing software step generation.
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