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On 7/20/2012 5:37 PM, Karl Schmidt wrote:
> On 07/20/2012 11:47 AM, Jon Elson wrote:
>> Charles Steinkuehler wrote:
>>> My current plan is to bit-bang GPIO pins based on code from the
>>> parallel port driver, but adding a bit of electronics would
>>> probably make things much easier.
> 
> What would the "bit of electronics" look like? Most of the single
> chip uP have hardware pulse generators built in that could easily
> generate the stepper pulses without jitter. Those chips are under
> $1 these days...
> 
> Lattice now has a 1000 logic cell FPGA with built in configuration
> ROM and lots of other goodies for less than $2 .. (twice that in
> single quantities from digikey )  there is enough room to put a 
> softcore CPU to talk to the controlling system etc..

Yeah, I've been helping Tim (a mutual friend) write some VHDL code for
the Lattice parts, which look pretty sweet.

I'd probably use some form of programmable FPGA/CPLD under $10 or so,
and right now the Lattice Ice parts are looking like the best bang for
the buck.  Having even a little bit of real hardware makes stepgen and
encoder monitoring a lot simpler than bit-banging in SW.  Plus most of
the micro-controllers don't have real (or very many) encoder inputs,
and can run out of timers fairly quick.

There's still level translation, isolation, and protection to deal
with, but that can be scaled to the task (ie: I'd put a lot more money
into protecting I/O headed to mains-driven servos than a RepRap
powered from the same 12V supply as my CPU).

> If I have this pictured correctly - the controlling Linuxemc system
> would run the outer servo loop - and the hardware would generate
> the pulses for steppers?
> 
> Hardware cost is no longer an issue.

...as long as I can get it to work.  If not, you'll have to wait until
the atom class chips get down to the Raspberry Pi pricing level.  :)

- -- 
Charles Steinkuehler
[email protected]
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