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On 12/2/2012 8:38 PM, Peter C. Wallace wrote:
> On Sun, 2 Dec 2012, Charles Steinkuehler wrote: [1] Ugly in this
> context means statically supporting one board (instead of
> dynamically allocating state memory and creating linked lists of
> the boards found) and probably not supporting x86 I/O ports 
> (required for the PLX based Mesa cards).
> 
> 
>> BTW I/O ports are not required for accessing the PLX cards (the
>> bridge chip registers can be accessed as I/O or memory)

Hmm...I was going based on the code in the hm2_pci_probe routine that
copies the start of BARs 1 and 2 (both I/O regions) to
board->ctrl_base_addr and board->data_base_addr.

I haven't dug through the rest of the driver code, but I didn't see
anywhere else that looks like it is mapping memory regions, and it
looked like you're using the PLX chip to configure the FPGA.

I am hoping to not have to modify the driver code much (mostly just
put some rtapi_ prefixes in front of the linux kernel pci routines and
structures).

Note that it's not a problem to access I/O regions, it's just not
something I need to do for the 5i25, so it won't be the first thing I
get to.  :)

...well, it could be problematic accessing I/O on non-x86 platforms
(I'm still reviewing cross-platform handling of PCI I/O regions), but
I figure that's not a bridge that needs to be crossed right now.  I
don't think anyone is going to be plugging their 5i20 into a Raspberry
Pi or BeagleBone anytime soon, although many non x86 platforms *DO*
support PCI, so it may need to be addressed someday.

- -- 
Charles Steinkuehler
[email protected]
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