Most of the mistakes are by the design engineers and not the pcb designers.
The mistakes are:
* Mixing of I/O devices with clocks, processors and similar noisy
digital devices
* Inadequate power/ground isolation of noisy digital devices
* Inadequate I/O filtering
* Failure to shunt ESD and EFT on I/O lines to chassis ground (not
digital ground)
* High impedance ground traces (too narrow and/or too long)
* Connecting I/O shields to the pcb and not to the chassis
* Inadequate physical isolation of power line filters from noisy
circuits and traces
Richard Woods
----------
From: rehel...@mmm.com [SMTP:rehel...@mmm.com]
Sent: Friday, January 21, 2000 7:48 AM
To: emc-p...@majordomo.ieee.org
Subject: EMC Circuit Board Design
Dear List-Members,
I am requesting information/opinions/etc. on the following:
When circuit boards are designed, what are the common mistakes that
the
circuit board designers make regarding EMC (multi-layer boards in
particular)?
You can respond to me directly but I would prefer a response to the
list as
I believe that the question is of interest to many on this
list-server. In
either event I will compile the responses and resend the compilation
later.
Thanks for your time,
Bob Heller
3M Company
---------
This message is coming from the emc-pstc discussion list.
To cancel your subscription, send mail to majord...@ieee.org
with the single line: "unsubscribe emc-pstc" (without the
quotes). For help, send mail to ed.pr...@cubic.com,
jim_bac...@monarch.com, ri...@sdd.hp.com, or
roger.volgst...@compaq.com (the list administrators).
---------
This message is coming from the emc-pstc discussion list.
To cancel your subscription, send mail to majord...@ieee.org
with the single line: "unsubscribe emc-pstc" (without the
quotes). For help, send mail to ed.pr...@cubic.com,
jim_bac...@monarch.com, ri...@sdd.hp.com, or
roger.volgst...@compaq.com (the list administrators).
