Hi Chris:
> To me, it's sort of funny in that it just says that the Creepage and
> Clearance distances do not apply on inner layers of void free PCBs.
> That's nice; but I can't find where a distance is specified. I mean, I
> would think that there should be some minimum distance between an AC line
> and a 5V SELV line on an inner layer of the board!!!!
>
> Our layout guy has a military specification that specifies insulation for
> 300-500V circuits. It specifies .100" on external layers and .010" on
> internal layers...which would work out to a factor of 10 reduction between
> surface layers and inner layers
Ideally, the conductors of inner layers of printed
wiring boards are imbedded in void-free solid
insulation.
For Basic Insulation, there are no requirements for
distance through solid insulation.
For Supplementary Insulation, IEC 60950 and maybe
other standards specify a minimum distance of 0.4 mm
(regardless of voltage) through the solid insulation.
The principal property of any insulation is that of
electric strength. Electric strength is the maximum
volts per unit distance at which the insulation will
not fail (break down). The electric strength of
solid insulations are typically at least two orders
of magnitude greater than that of air insulation.
Consequently, the distance between conductors of
inner layers of a printed wiring board can be quite
close together compared to those conductors on the
surface of the printed wiring board.
One theory of solid insulation failure is that of
partial discharge in air-filled voids.
The problem of thin solid insulation is that the
volts per unit distance can be quite high. Recall
that an electric field exists between any two
conductors. The electric field is defined by a set
of equipotential lines within the solid insulation.
The thinner the insulation, the closer the
equipotential lines.
Air breaks down when the absolute potential exceeds
about 300 V rms AND the potential per unit distance
exceeds about 1500 V rms/mm.
So, if the voltage across an insulator exceeds
300 V rms, and the equipotential lines are closer
than 1500 V/mm, then partial discharge can occur
in a void in solid insulation. If the partial
discharge is allowed to continue, then the air in
the void will break down (arc).
The heat of the arc will decompose the insulating
material, resulting in a carbon path through the
void. This effectively shorts out a part of the
solid insulation. The equipotential lines are
re-distributed, and the remaining solid insulation
has a higher V/mm, at least near the void. The
higher V/mm can cause other voids to partial
discharge and arc. We then have a cascading effect,
with the end-result being a carbon path through the
solid insulation.
(I've assumed the insulating material is organic;
inorganic materials don't necessarily have this
same failure mechanism, which is why many high-
voltage insulators are porcelain.)
Best regards,
Rich
> From owner-emc-p...@majordomo.ieee.org Tue Aug 13 15:44:23 PDT 2002
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> From: j...@aol.com
> Message-ID: <15f.12358e09.2a8ac...@aol.com>
> Date: Tue, 13 Aug 2002 16:09:32 EDT
> Subject: Re: Creepage on PCB Internal Layers
> To: chris.maxw...@nettest.com, richard.pa...@exgate.tek.com,
> emc-p...@majordomo.ieee.org
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> --part1_15f.12358e09.2a8ac17c_boundary
> Content-Type: text/plain; charset="US-ASCII"
> Content-Transfer-Encoding: 7bit
>
> In a message dated 8/13/2002, you write:
>
>
> > To me, it's sort of funny in that it just says that the Creepage and
> > Clearance distances do not apply on inner layers of void free PCBs.
> > That's nice; but I can't find where a distance is specified. I mean, I
> > would think that there should be some minimum distance between an AC line
> > and a 5V SELV line on an inner layer of the board!!!!
> >
> > Our layout guy has a military specification that specifies insulation for
> > 300-500V circuits. It specifies .100" on external layers and .010" on
> > internal layers...which would work out to a factor of 10 reduction
> between
> > surface layers and inner layers
>
>
> Hi Chris:
>
> I work with EN 60950, not EN 61010-1, so my comments here are only general.
>
>
> In EN 60950 the creepage and clearance requirements can be eliminated for
> inner layers, but all other requirements for the relevant insulation still
> apply. For example, both supplementary insulation and reinforced
> insulation
> still require a minimum of 0.4 mm through solid insulation. Also, any
> relevant hipot tests for the insulation in question still apply.
>
> In general, a well constructed circuit board will have extraordinary
> insulation between traces on the same layer, due to the high dielectric
> strength of the prepreg and the bonding agents that are used. Even a
> separation .002" will, in theory, have a dielectric strength of more than
> 1000 volts.
>
> However, I prefer to be cautious here, in the event that a defect creates a
> small air gap in the isolation area. I would suggest using as large a gap
> as
> you can reasonably achieve, even if the regulations call out no minimum or
> a
> minimum of only 0.4 mm. The 0.8 mm target that you have nominated sounds
> OK
> to me, but if you can bump it up to 1.0 mm or more, that would be nice.
>
>
> Joe Randolph
> Telecom Design Consultant
> Randolph Telecom, Inc.
> 781-721-2848
> http://www.randolph-telecom.com
>
> --part1_15f.12358e09.2a8ac17c_boundary
> Content-Type: text/html; charset="US-ASCII"
> Content-Transfer-Encoding: 7bit
>
> <HTML><FONT FACE=arial,helvetica><FONT SIZE=2>In a message dated
> 8/13/2002, you write:<BR>
> <BR>
> <BR>
> <BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT:
> 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">To me, it's sort of funny in that
> it just says that the Creepage and Clearance distances do not apply on inner
> layers of void free PCBs. That's nice; but I can't find where a
> distance is specified. I mean, I would think that there should be some
> minimum distance between an AC line and a 5V SELV line on an inner layer of
> the board!!!!<BR>
> <BR>
> Our layout guy has a military specification that specifies insulation for
> 300-500V circuits. It specifies .100" on external layers and .010" on
> internal layers...which would work out to a factor of 10 reduction between
> surface layers and inner layers</BLOCKQUOTE><BR>
> <BR>
> <BR>
> Hi Chris:<BR>
> <BR>
> I work with EN 60950, not EN 61010-1, so my comments here are only
> general. <BR>
> <BR>
> In EN 60950 the creepage and clearance requirements can be eliminated for
> inner layers, but all other requirements for the relevant insulation still
> apply. For example, both supplementary insulation and reinforced
> insulation still require a minimum of 0.4 mm through solid insulation.
> Also, any relevant hipot tests for the insulation in question still apply.<BR>
> <BR>
> In general, a well constructed circuit board will have extraordinary
> insulation between traces on the same layer, due to the high dielectric
> strength of the prepreg and the bonding agents that are used. Even a
> separation .002" will, in theory, have a dielectric strength of more than
> 1000 volts.<BR>
> <BR>
> However, I prefer to be cautious here, in the event that a defect creates a
> small air gap in the isolation area. I would suggest using as large a
> gap as you can reasonably achieve, even if the regulations call out no
> minimum or a minimum of only 0.4 mm. The 0.8 mm target that you have
> nominated sounds OK to me, but if you can bump it up to 1.0 mm or more, that
> would be nice.<BR>
> <BR>
> <BR>
> Joe Randolph<BR>
> Telecom Design Consultant<BR>
> Randolph Telecom, Inc.<BR>
> 781-721-2848<BR>
> http://www.randolph-telecom.com</FONT></HTML>
>
> --part1_15f.12358e09.2a8ac17c_boundary--
>
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