Yes, Thanks Richard ************************ By the way...Rich Woods...Tektronics (Richard Payne's company) also makes fiber optic power meters. Sorry that I forgot to mention them in my reply earlier today. Yes, they're a competitor of ours; but their compliance guy is nice enough to answer my questions :-) ************************** Now back to the issue at hand.
That's what I was looking for (the statement in paragraph 6.7 of EN 61010-1) The copy that I have has the amendments separate. I found it in Amendment 2 as you stated. To me, it's sort of funny in that it just says that the Creepage and Clearance distances do not apply on inner layers of void free PCBs. That's nice; but I can't find where a distance is specified. I mean, I would think that there should be some minimum distance between an AC line and a 5V SELV line on an inner layer of the board!!!! Our layout guy has a military specification that specifies insulation for 300-500V circuits. It specifies .100" on external layers and .010" on internal layers...which would work out to a factor of 10 reduction between surface layers and inner layers. Using that same reasoning, I was looking at a circuit that needs 8mm of creepage on a surface layer (.314"). Would I be "safe" in allowing 0.8mm (0.0314") of distance on an inner layer? Anybody have any thoughts on this one. Chris Maxwell | Design Engineer - Optical Division email chris.maxw...@nettest.com | dir +1 315 266 5128 | fax +1 315 797 8024 NetTest | 6 Rhoads Drive, Utica, NY 13502 | USA web www.nettest.com | tel +1 315 797 4449 | > -----Original Message----- > From: richard.pa...@exgate.tek.com [SMTP:richard.pa...@exgate.tek.com] > Sent: Tuesday, August 13, 2002 3:17 PM > To: Chris Maxwell; emc-p...@majordomo.ieee.org > Subject: RE: Creepage on PCB Internal Layers > > Hi Chris: > > The 2nd edition of 61010 has the statement in clause 6.7: > > There are no CLEARANCE or CREEPAGE DISTANCE requirements for the interior of > void-free moulded parts, including the inner layers of multi-layer printed > circuit boards. > > > UL3111 has the following UL deviation from the 1st edition of 61010: > > 6.7 Eliminate spacing requirements on inner layers of multi-layer printed > circuit boards > > The inner layers of a multilayer printed circuit board are considered to be > void-free molded parts. The CLEARANCES and CREEPAGE DISTANCES specified in > Annex D do not apply to these inner layers. (See Note 2 of Annex D, > subclause D.2.1 of Amendment 1). > > Richard > > Richard Payne > Tektronix Inc. > Product Safety Engineering > V: (503) 627-1820 > F: (503) 627-3838 > E: richard.pa...@tektronix.com > > ------------------------------------------- This message is from the IEEE EMC Society Product Safety Technical Committee emc-pstc discussion list. Visit our web site at: http://www.ewh.ieee.org/soc/emcs/pstc/ To cancel your subscription, send mail to: majord...@ieee.org with the single line: unsubscribe emc-pstc For help, send mail to the list administrators: Ron Pickard: emc-p...@hypercom.com Dave Heald: davehe...@attbi.com For policy questions, send mail to: Richard Nute: ri...@ieee.org Jim Bacher: j.bac...@ieee.org All emc-pstc postings are archived and searchable on the web at: http://ieeepstc.mindcruiser.com/ Click on "browse" and then "emc-pstc mailing list"
