Hi Brian:
> The environment being considered is a switching power supply. The technique
> that safety agencies use to simulate a SFC on a power FET does not seem,
> IMHO, to simulate the actual failure mode of the device. To wit: when the
> mosfet fails short, it blows itself open; so the amount of current "sucked"
> out of mains, e.g., the PFC FET, would probably open the component after a
> few input cycles. But if I apply a direct mechanical short (source to
> drain), current is being forced to flow until the fuse blows, or until some
> series trace or component opens.
The shorting of a component does not test that
component. Instead it tests the remainder of
the circuit for (safety?) weaknesses in the
event of a short (or near-short) of that
component.
I suppose the opening of a circuit does test
for the component failing in the open condition.
But, the effect of the open-circuit is to test
the remainder of the circuit for (safety?)
weaknesses.
So, shorting or opening of a component does not
test the component but other parts of the
circuit.
In general, the termination of fault tests
should be not only repeatable, but should be
understood so that the parameters that make
the termination repeatable are under control.
The operation of a fuse is a good termination
of a fault test.
A cascaded fault of another component may not
be a good termination of a fault test because
the "safe" termination may depend on unknown
or uncontrolled component characteristics.
> The Bad: some FETs fail very violently, and can actually be a fire hazard
> and/or shock hazard in open-frame switchers; but if the FET itself does not
> provide the short circuit, we will never know....
Switchers generally drive the switching FETs
with a pulse-width-modulated waveform. One
way to introduce a fault that tests the FET is
to simulate a 100% duty cycle pulse by applying
a dc voltage of the same voltage as the PWM
signal. This will turn on the FET continuously,
and you should get your spectacular failure.
> The Good: providing a "continuous" (mechanical) short will reveal if there
> are other components in the current path that could be cause the unit to
> fail in an unsafe mode. Although, according to QA records, these components
> have never failed, so it can be both demonstrated by design equations and
> empirical evidence that the SFC test does necessarily demonstrate anything
> relevant...
Uh, no... I don't think you want to base your
fault-condition safety on empirical data that
the fault will not occur.
I have never seen the fault of basic insulation
in the field, but we nevertheless account for
the failure of basic insulation with either
grounding or supplemental insulation.
There is nothing like a test.
> The Ugly: Safety testing results in design corrections that do not increase
> product safety.
I would argue this point. I have not seen undue
design corrections due to a fault test.
> So would it be legitimate to over-drive the gate, forcing short circuit
> current to flow through the FET, but not to apply a mechanical short across
> the component?
Yes!
But, unfortunately, some components do not lend
themselves for such testing. Capacitors are a
good example -- almost impossible to induce a
fault.
Best regards,
Rich
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