I've been reading through all your answers and comments like through a good
book.  I still have no idea how the story will end!

To follow-up on Gert Gremmen's comments, the kind of eval board I am
adressing here is the kind with a whole bunch of connectors and test points
installed directly on the PCB surface, to monitor clock signals or to
inject voltage biases from external sources while the IC under test is
being investigated.  Of course any eval board could be placed inside an
enclosure with shielded connectors for everything, but I've never seen
that.  And of course, doing so for an item not intended to be a finished
product would add a lot of design cost that would lead to an unaffordable
price for the eval boards, essentially killing the purpose.

The purpose of my enquiry was not to find a way to go around directives and
standards to maybe put humans or licensed communications in danger, but was
to find out what was the actual regulatory framework that adresses these
very specific kits.  And from all of your generous comments, the only
conclusion I can draw today is: there is none.  No authority (in Europe at
the least) has ever published specific guidelines on the subject.  So do
what you think is right, but be prepared (with a strong enough legal
department) to defend your decisions.  Although I'm really holding on to
Brian Kunde's interpretation of apparatus and end-user as described in the
Guide for the EMC Directive.

I am suprised at the lack of FCC-sided comments.  Is this because you think
FCC Form 740 option 3. "The described equipment is being imported in
limited quantities for testing and evaluation for compliance with technical
requirements or marketing suitability. The equipment will not be offered
for sale or otherwise marketed." is sufficient to go through customs with
an untested eval board?

John B.


On Tue, Nov 5, 2013 at 9:34 AM, ce-test, qualified testing bv - Gert
Gremmen <g.grem...@cetest.nl> wrote:

> Your philosophy is mine but for one thing:
>
> It's not because a product cannot meet requirements as put on the market
> that it should be excluded ..
>
>
> It could for example be sold in an enclosure, so as to meet ESD
> requirements.
> It's not a absolute requirement for these board to be sold
> as a bare PCB. It has consequences for the prices of course but
> that is valid for each device, not for development boards only.
>
> And it is not because you can touch a chip, that it need to be
> tested. Standards speak about likely to be touched in normal use.
> Connector internal pins on my Ipad are accessible too, but most standards
> do
> not include them for ESD testing. It may be wise to do so, but that is
> another story.
>
>
> BTW did anyone obtain a satisfactorily answer from Farnell or any other
> seller ?
>
> Your opinion about the EC in these, in casu their authors, is not mine.
> EC texts do generally excel in quality, what need not be the same as
> clear to us,  or in line with our needs. Note that they are
> addressed to the member states and their legal advisors and not to
> the end users. If unclear on a special subject, than it
> certainly is the case because the subject is not well enough defined, or
> it would open a way to avoid requirements by what i call
> smart naming or smart selling.
>
>
>
>
> Regards,
>
> Ing.  Gert Gremmen, BSc
>
>
>
> g.grem...@cetest.nl
> www.cetest.nl
>
> Kiotoweg 363
> 3047 BG Rotterdam
> T 31(0)104152426
> F 31(0)104154953
>
>  Before printing, think about the environment.
>
>
>
> -----Oorspronkelijk bericht-----
> Van: Piotr Galka [mailto:piotr.ga...@micromade.pl]
> Verzonden: Monday, November 04, 2013 6:23 PM
> Aan: EMC-PSTC; ce-test, qualified testing bv - Gert Gremmen
> Onderwerp: Re: [PSES] EMC requirements for developer/evaluation boards
>
> Hi Gert,
>
> > To Piotr: ESD test are normally carried out on enclosure and connector
> > shielding, not to internal circuits.
> > HCP and VCP discharge are designed for this.
> >
>
> My logic is:
> The idea of ESD test is to check possible events which can happen in
> normal use of device.
> The possible source of ESD are human fingers.
> Human fingers touches enclosure and not internal circuits because
> enclosure is between fingers and internal circuits.
> So ESD is tested on enclosure and on HCP and VCP = all expected ESD that
> can happen to and near device.
> If device has plastic enclosure than in real ESD to something near device
> has higher probability than to device (which is close to 0%).
>
> If there is no enclosure than human fingers can touch directly internal
> circuits so following the idea of testing all possible ESD events in my
> opinion ESD should be also tested to internal circuits. I think that for
> such device the ESD to internal circuits has much higher probability than
> to something near (HCP and VCP). There is no idea to testing something less
> probable and not testing something more probable.
>
> If the prototype board is to be used only in ESD protected environment
> than testing ESD to internal circuits can have no sense but testing ESD to
> HCP and VCP also has no sense.
>
> But generally I think that prototype board should be excluded from EMC at
> all and it should be written in the first EMC directive version long time
> ago.
> When I first time read EMC (in 2002 - two years before we (Poland) joined
> EU) the question about prototype board was my first thought.
> Being not clear solved in directive that subject makes me to have clear
> opinion about its authors.
>
> Best Regards
> Piotr Galka
>
> -
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