Hi Amund,

 

If you have the space on the board then a ground fill around the perimeter (on 
all layers) probably won’t do any harm. Whatever ground fill strategy you 
decide on for the signal layer I would make sure it is well connected with vias 
to both of the adjacent planes along the edge nearest to the signals and around 
the perimeter of the PCB. The distance between these vias probably isn’t that 
critical but you often see the figure of wavelength/20 or wavelength/10 used as 
a guideline. For a digital signal you could use 0.35/Trise as a rule of thumb 
for working out the frequency. Lambda = c/f takes care of the rest.

 

Edge plating (as Ken points out) is an option but obviously adds cost to the 
PCB.

 

Part of the aim will be to maintain the correct characteristic impedance of 
your transmission line to help ensure good signal quality. You could model the 
PCB stackup and trace geometry in something like Polar or Hyperlynx (this free 
tool <https://www.eeweb.com/tools/edge-coupled-stripline-impedance>  doesn’t 
account for a co-planar ground) and see how far away the co-planar ground needs 
to be to maintain the correct impedance. Or just choose an arbitrarily large, 
conservative (small c) number like 10h (h being height of the smallest gap 
between trace and plane).

 

If you have noise leakage, that would suggest that your “differential” lines 
might not be as differential as you think. Unequal rise/fall times and skew 
between rising and falling edges will create common mode noise on these pairs. 
This is usually a fundamental characteristic of the driver circuit itself and 
there’s not much you can do about it. May be worth trying a HF common mode 
choke at the source – Wurth, Murata and TDK make good ones.

 

Local ground via where your HF signals transition between layers to ensure that 
the return path currents can transfer from one side of the plane to the other 
(skin effect). This should be balanced, that is equidistant between the traces, 
or use two in symmetrical layout, to avoid imbalance in parasitic capacitance. 
You may also want to think about via “anti pads” to improve your impedance 
matching.

 

What bus technology are you using for these high speed traces?

 

HTH

James

 

 

James Pawson

EMC Problem Solver

 

Unit 3 Compliance

EMC Testing / Design for EMC / Problem Solving / Pre Compliance / Consultancy / 
Environmental & Vibration

 <http://www.unit3compliance.co.uk/> www.unit3compliance.co.uk -- 07811 139957

Opening Hours: Tuesday to Friday, 0830 to 1800. Closed Monday.

 

From: Amund Westin <am...@westin-emission.no> 
Sent: 19 February 2020 06:51
To: EMC-PSTC@LISTSERV.IEEE.ORG
Subject: [PSES] SV: [PSES] Ground copper fill on signal layer on multilayer PCB

 

Hi Ken

 

No, I have not considered edge-plating. I’ll look into this now.

We have some high frequency noise (400-500MHz) from differential lines leaking 
out from an inner layer of a multilayer pcb. Edge-plating might be a good 
solution.

Thanks for the tip.

 

BR
Amund

 

Fra: IBM Ken 
Sendt: 18. februar 2020 23:18
Til: EMC-PSTC@LISTSERV.IEEE.ORG <mailto:EMC-PSTC@LISTSERV.IEEE.ORG> 
Emne: Re: [PSES] Ground copper fill on signal layer on multilayer PCB

 

Hi Amund!  Have you also considered edge-plating?  Are you trying to reduce 
radiated noise outside your product, or cross-talk within the product (or both)?

 

On Tue, Feb 18, 2020 at 3:03 AM Amund Westin <am...@westin-emission.no 
<mailto:am...@westin-emission.no> > wrote:

Between two solid ground planes, we have a signal layer, routing high speed 
differential lines.

 

What do you recommend: 

I.      fill the remaining area with copper in the signal layer 
II.     fill only the border of the layer (5mm ground copper trace around the 
layer edge)
III.    no fill at all

 

 

Best regards

Amund

 

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