The relationship between the FPGA pins, the parport, and the pin headers
is documented in "pluto_servo.pin" in CVS. There are some
one-transistor inverters for some of the parport signals. There's
clock source (40MHz) and voltage regulation (there, you'd be better off
following the datasheet than the existing board layout!).
Here are some notes I wrote on the board:
http://emergent.unpy.net/01165081407
Reportedly the design is 4-layer, presumably the inner two layers are
GND and supply. Altera's datasheets propose a separate VCC_core and
VCC_io, while the pluto-p board appears to use a 3.3V supply for both.
I question the value of cloning the pluto board, compared to a new board
design with:
* More sensible I/O headers
* More powerful FPGA from current FPGA line
* Correct power supply
* Provision for mounting
In many ways, the upcoming mesanet board that SWP mentioned seems to be
that board. About the only advantage you'd have with a clone board is
that you would avoid any firmware development time.
Jeff
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