On Wed, 10 Dec 2008, Jon Elson wrote: > Date: Wed, 10 Dec 2008 15:03:57 -0600 > From: Jon Elson <[EMAIL PROTECTED]> > Reply-To: "Enhanced Machine Controller (EMC)" > <emc-users@lists.sourceforge.net> > To: "Enhanced Machine Controller (EMC)" <emc-users@lists.sourceforge.net> > Subject: Re: [Emc-users] Write error with hostmot2 and 7i43 board > > Peter C. Wallace wrote: >> >> >> I wasted 2 days fscking around with those cards (NetMos = MOSChip 9805 based) >> I had no trouble getting them into EPP mode, they just dont work right in EPP >> mode. I got write to work but they seem to sample the read data on the >> leading >> edge of the strobe, this is contrary to the EPP specs I've read and every >> other EPP capable parallel port I have tested. For some more advanced >> features >> of HostMot2 to work properly, reads must be qualified by a strobe as some >> read >> have side effects (reading FIFOs for example). There is no reliable way to >> make this work with the MOSChip parts. I hate to admit defeat as these are by >> far the most common PCI parallel port chips but I give up on MosChip cards. >> >> > Obviously, the par port chip has to wait for a signal from the slave > device to indicate the data is present before sampling it. > I had similar problems with some other PCI boards, and found that I was > gettting crosstalk from strobes and data lines onto the WAIT signal, > causing the read operation to end and sample too early. I have been > manually adding a bunch of termination resistors to my boards until I > can respin the PCBs. Never needed this with the motherboard par ports, > but the timing, logic levels, etc. of the PCI boards are different.
With the 9805, I can see that the strobe ends in response to my wait signal, but the data is sampled somewhere around the falling (leading) edge of the strobe. I thought about an error caused by the port seeing /wait asserted too early so even tried putting a fair sized cap at the parallel port end of /wait, this slowed the handshake, but did not help reading tha data at the right time. Only way I could thnk of making the NetMos cards read right is by supplying read data when READ is high, but thats too ugly (bus conflicts etc) to consider seriously. > > I did find one motherboard that had a problem in the ISA interface > chip. I could watch the EPP signals and see the data lines changing > while the strobe was active. The only explanation I could come up with > was that every couple hundred EPP cycles, the ISA interface would fail > to put the CPU into a wait state, and when the CPU wrote again to the > EPP data register, it would change the data being sent. No way to fix > that one either! No, sounds like a timing error in the wait state insertion logic > > Jon > > ------------------------------------------------------------------------------ > SF.Net email is Sponsored by MIX09, March 18-20, 2009 in Las Vegas, Nevada. > The future of the web can't happen without you. Join us at MIX09 to help > pave the way to the Next Web now. Learn more and register at > http://ad.doubleclick.net/clk;208669438;13503038;i?http://2009.visitmix.com/ > _______________________________________________ > Emc-users mailing list > Emc-users@lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/emc-users > Peter Wallace Mesa Electronics (\__/) (='.'=) This is Bunny. Copy and paste bunny into your (")_(") signature to help him gain world domination. ------------------------------------------------------------------------------ SF.Net email is Sponsored by MIX09, March 18-20, 2009 in Las Vegas, Nevada. The future of the web can't happen without you. Join us at MIX09 to help pave the way to the Next Web now. Learn more and register at http://ad.doubleclick.net/clk;208669438;13503038;i?http://2009.visitmix.com/ _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
