Peter,
I found something interesting while checking to get your answers. Presiously
I was only jogging X and Y, and did not get any errors. This time I tried Z
as well. When I jog the Z axis I get the TRAM write error. That would
explain why I get the error when running a G-Code program, but not when
jogging. The test program I was using was 3D_Chips, which of course uses the
Z axis.
Here are the answers to your questions.
LED states
PWR DONE INIT
Start-up Yellow Red Red
EMC Start Yellow Off Off
After Error Yellow Off Off
Stop EMC Yellow Off Off
Basically the LED states never change once EMC is run for the first time.
As for cycling power, I have done both a warm reboot and cold reboot. No
difference.
I will check to see if there is anything different in the configuration of Z
relative to X and Y.
Regards,
Eric
Well, Sebastian confirmed that the TRAM write error is an EPP timeout error,
but the CPLD error indicates something more global is wrong. Is it possible
you have a power supply issue?
EPP timeout means that the card did not respond to a address or data strobe
by de-asserting /Wait within 10 uSec. Normal FPGA timing is 300 nS for this
time, more than 10 Usec likely means that the card is unplugged, powered
down or some how locked-up. The CPLD error when attempting to re-program the
FPGA makes some kind of power or lock-up problem more likely the culprit.
What would be helpful to me is this information:
What are the LED states when you get the TRAM error?
What are the LED states when you get the CPLD error?
When you say fresh boot, are you cycling the power?
Does reset without cycling the power allow you to reprogram the FPGA?
Peter Wallace
Mesa Electronics
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