On Thu, 17 Sep 2009, Eric H. Johnson wrote:
> Date: Thu, 17 Sep 2009 15:43:48 -0400
> From: Eric H. Johnson <ejohn...@camalytics.com>
> Reply-To: "Enhanced Machine Controller (EMC)"
> <emc-users@lists.sourceforge.net>
> To: "'Enhanced Machine Controller (EMC)'" <emc-users@lists.sourceforge.net>
> Subject: Re: [Emc-users] Questions about the parallel port
>
> David,
>
> If you are referring to FPGA type PCI bus boards like the Mesa products, you
> are not comparing apples to apples when discussing speed. In the case of the
> parallel port, the base thread which handles the I/O is run on the CPU. In
> the case of an FPGA board, the base thread is effectively run on the FPGA
> board. It handles counting of individual pulses from the encoder or
> generating the pwm or step outputs. The servo thread then just comes around
> periodically to read the current count, or set a velocity value for the pwms
> or step generation.
>
> For example, the Mesa 7i43 communicates over the parallel port, but as an
> FPGA device, it can handle much higher speed counters (encoders), pwms and
> step generators than the parallel port can by itself.
>
> HTH,
> Eric
>
This is also true of the Pico systems parallel port interfaced products. With
smart I/O, the parallel port update rate (from 1 KHz to perhaps 4 KHz) is fine
for servo or step generation when all the high speed logic is done locally in
the external FPGA or processor.
Where the parallel port device becomes a limiting factor, even with a smart
external device, is when very high sample rates are required (say 5 KHz
and >), or lots of axis or lots of fast realtime I/O is required. Then a PCI
or some other faster interface is needed. Unless you have a lot of I/O or
linear motors, the PCI interfaced cards are not a requirment.
Peter Wallace
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