David Braley wrote: > > Well, it just goes to show how naive I am about all of this stuff. I > only barely understand what the two of you just said. I think what you > are suggesting is that some of the work needed to control an axis is > somehow off-loaded to the smarter FPGA device, be it a faster parallel > port, or PCI bus I/O device. This of course, effectively freeing up the > CPU on the computer. I'm just guessing here. > Yes, exactly. An FPGA can be set up to count out time in, say, 25 ns units, and put out step pulses every so many ticks of that clock. That can give about 1000 times finer grain timing. > I was under the impression that the PC running EMC did most of the heavy > lifting. It CAN, but there are major benefits to letting more suitable hardware take over the demanding timing tasks. > This means that at a modest 100ipm of table travel speed, the position > pulse stream is 16,666.67 pulses per second. I just had trouble > imagining a parallel port dealing with something like this. Even if the > table encoder position output stream was fed to a counter, how can the > system know where it's at without looking (through the parallel port) at > the output of the counter value at least 16K+ times a second? > Well, if the base thread is running at 32 KHz, you can put out step pulses at 16 KHz. But, at 99 IPM, step pulses would be jumping between 16 KHz (every other tick of BASE_THREAD) and the next lower step (every third tick) or 10.6 KHz. That is an enormous jump in step rate, leading to loss of stepper sync, of just ragged operation. That's the advantage of making hardware do easily what software struggles to do badly.
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