On Tue, 16 Mar 2010 17:25:46 -0400, you wrote: >On Tue, Mar 16, 2010 at 4:45 PM, Steve Blackmore <st...@pilotltd.net> wrote: > >> Not quite - press Feed hold, stop spindle then jog -X to clear tool, >> then +Z to get out of bore, replace tip. Start spindle, press cycle >> start. Tool did a combined XZ move at current feed rate to where it >> stopped then continued from there. > >That's a great example how it might be tricky in general. In your case, >a simultaneous XZ move was appropriate, as would be Z followed by X, >but not X followed by Z. In another configuration (e.g. facing) the opposite >would have been true, and I can imagine cases where neither would work >(e.g. a center stub in an undercut bore hole, requiring a Z->X->Z->X move).
X followed by Z would have been OK, as would Z followed by X from the position I restarted from. You need to think where the tool is before you press Cycle start and position accordingly. If you know it's ALWAYS going to do a combined move it's not hard to move the tool to a suitable position. >This doesn't mean that it isn't a desirable feature that should be implemented, >just that it isn't as simple as you portray it to be. It is very simple - you merely have to think before restarting. If it crashes, you didn't think hard enough ;) >Since a full >interference detection >doesn't seem sensible, it'd have to be some big fat warning window >that it's your >responsibility to clear the tool path. A big fat warning window, why? Fanuc's behave the same way, no warning windows there? It's the operators responsibility to ensure he knows how to operate his machine properly. Please no "Nanny State" madness, if anyone does go down that route, please ensure warning can be turned off, nothing more annoying than "are you sure" messages. Steve Blackmore -- ------------------------------------------------------------------------------ Download Intel® Parallel Studio Eval Try the new software tools for yourself. Speed compiling, find bugs proactively, and fine-tune applications for parallel performance. See why Intel Parallel Studio got high marks during beta. http://p.sf.net/sfu/intel-sw-dev _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
