On 19 February 2011 10:35, Roland Jollivet <roland.jolli...@gmail.com> wrote:
> Surely there is no need to have a 32 bit counter? A 16 bit counter should > suffice? Yes and no. The Mesa FPGAs actually use a 16 bit counter, but this is expanded to 64 bits by the EMC2 drivers, then re-exported to the HAL pins as 32 bits. I think the policy is that all encoder counters in EMC2 are 64 bits internally. The reason is that the encoder counts are used to track the positions of the axes, typically axis position is simply encoder counts x scale. There is absolutely no expectation that an encoder counter will roll-over at an integer number of base units, and in fact there is no requirement for the encoder scale to be an integer, less still an integer factor of encoder counts. An example of where this matters is the bldc component, which uses the encoder counts to derive the absolute position of the motor rotor. If the motor has a 1000 count encoder (ie not an integer factor of 2^32) then when the encoder rolls-over the angle calculation will be incorrect, and the motor will either stop, lose torque or start running in the wrong direction. Originally that component used a 32 bit counter, but was later expanded to 64 bits. 32 bits can track a 3000rpm motor for a few hours. 64 bits can track one for half a million years. The former latter is too long, but the former is too short, and that is worse. There would be an option to check the current axis position against the previous and check for a 31-bit rollover (it's signed) but the computational overhead of doing that is probably higher than simply shuffling a few more bytes through the adder. -- atp "Torque wrenches are for the obedience of fools and the guidance of wise men" ------------------------------------------------------------------------------ The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: Pinpoint memory and threading errors before they happen. Find and fix more than 250 security defects in the development cycle. Locate bottlenecks in serial and parallel code that limit performance. http://p.sf.net/sfu/intel-dev2devfeb _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
