On Fri, 18 Feb 2011 12:19:54 -0500, you wrote: >You may well be right Peter. But dragging the VIA chips into this >discussion reminds me of the debacles I experienced with both the VIA and >CYRIX chips of yore. Very poor quality and most of the mobo's died even >before the Packard Bell monitors that came with that 2 pallets of machines >we bought for the news dept. did.
I'll add another to your list of poor quality items - Gateway PC's ;) VIA chipsets were on the "unsupported by Mach3" for a good while. Very erratic clock was the perceived problem but it was actually something to with a bug in APIC. Give VIA their due, they did a considerable amount of work with Art and told him how to circumvent the problem in software. This was December 2007, on subsequent chipsets, AFAIK they fixed the problem. Steve Blackmore -- ------------------------------------------------------------------------------ The ultimate all-in-one performance toolkit: Intel(R) Parallel Studio XE: Pinpoint memory and threading errors before they happen. Find and fix more than 250 security defects in the development cycle. Locate bottlenecks in serial and parallel code that limit performance. http://p.sf.net/sfu/intel-dev2devfeb _______________________________________________ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
