On Wed, 17 Aug 2011, Maximilian H wrote: > Date: Wed, 17 Aug 2011 09:01:00 +0200 > From: Maximilian H <[email protected]> > Reply-To: "Enhanced Machine Controller (EMC)" > <[email protected]> > To: "Enhanced Machine Controller (EMC)" <[email protected]> > Subject: [Emc-users] Mesa 7i43 fpga internal input pull ups - could sb > synthesise another firmware for the 7i43 with pull downs for GPIO pins > please ? > > > Hello List, > > I have run into a problem with my new revision of my pcb which adapts a > 7i43 and a 7i33 to a machine of mine. > > Before I had W3 in the up position, which enabled the pull ups on the > 7i43. Then I inverted the polarity of the outputs in the hal layer,i.e. > the output signals where active low. > > While designing the new pcb I thought I'd get rid of the inversion of > the polarity in the hal layer and designed the output signals to be > active high. Turns out that this was a *bad* idea. > > Now I running into the same problem as Malte on the 11th of this month > in "[Emc-users] Mesa 7i43 hostmot and EMC2 exit"i,i.e. once emc2 unloads > the watchdogs bite, all output are reconfigured as input. The internal > pullup drive the pin high and all my outputs on the pcb are enabled. > > Now I was looking for a quick fix and found lines like these in the > 7i43.ucf. These are the pins that I use for outputs. Pin numbers are 24 > to 31 in the hal layer. > > 7i43u.ucf:NET "IOBITS<27>" LOC = "p27" | IOSTANDARD = LVCMOS33 | DRIVE > = 24 | SLEW = SLOW | PULLUP ; > > I am hoping that putting PULLDOWN here instead of PULLUP would solve my > problems. > Could somebody comment on that ? As anybody tried ? > > Could somebody synthesise a new firmware for me with these pins having > internal pulldown instead of pullups. > > Thanks > BR > Max.
This is possible but unfortunately its not a really good solution. The reason is that the FPGA pins will still float before the FPGA is configured. The choice of active Low outputs was done for two reasons: 1. The 50 pin I/O connectors are compatible with I/O module racks, like OPTO22 GrayHill, WRC or others 2. The FPGA has a pre configuration PULL_UP option so its easy to get a defined high state on the pins at power up. You can set the pulldown option in the .ucf file and disable the pre-config pullups on the 7I43, and it may work, but its not optimal. > > > > > ------------------------------------------------------------------------------ > Get a FREE DOWNLOAD! and learn more about uberSVN rich system, > user administration capabilities and model configuration. Take > the hassle out of deploying and managing Subversion and the > tools developers use with it. http://p.sf.net/sfu/wandisco-d2d-2 > _______________________________________________ > Emc-users mailing list > [email protected] > https://lists.sourceforge.net/lists/listinfo/emc-users > Peter Wallace Mesa Electronics (\__/) (='.'=) This is Bunny. Copy and paste bunny into your (")_(") signature to help him gain world domination. ------------------------------------------------------------------------------ Get a FREE DOWNLOAD! and learn more about uberSVN rich system, user administration capabilities and model configuration. Take the hassle out of deploying and managing Subversion and the tools developers use with it. http://p.sf.net/sfu/wandisco-d2d-2 _______________________________________________ Emc-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/emc-users
